Memory Array Connections Routed Through Control Gates for Dense Layouts
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Solution Overview
Problem
As memory cell density increases in memory devices, routing interconnections within the device becomes difficult, leading to challenges in fabricating and improving the efficiency of memory operations.
Innovation Solution
The implementation of connections that route through control gates and select gates within the memory device, allowing for improved interconnections and reduced fabricating costs by optimizing the layout of these connections on one side of the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density increases, then storage capacity improves, but routing interconnections becomes difficult
Solution Approach 1:
The connection structure is routed through the control gate, nesting the connection path within the existing gate structure. This allows the connection to pass through the control gate without requiring additional routing layers or external paths, thereby maintaining low routing complexity while supporting higher memory cell density
Solution Approach 2:
The connection is routed vertically through the control gate in the z-dimension rather than horizontally in the x-y plane. This dimensional transition allows connections to pass through overlapping regions without interfering with planar routing, enabling higher density without proportionally increasing routing complexity
2Adaptability or versatility
If more interconnections are added, then device functionality improves, but fabricating costs increase
Solution Approach 1:
The connection structure is merged with the control gate structure, combining two separate elements into a unified design. The connection is formed within the control gate's material layers and physical space, eliminating the need for separate connection structures and reducing overall fabrication complexity and cost
Solution Approach 2:
The control gate serves dual functions: it controls the memory cell operation and simultaneously provides a pathway for the connection to pass through. This multi-functionality reduces the total number of separate components needed, simplifying fabrication and reducing costs while maintaining full device functionality
Data Source
AI summary
Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.