Memory Array Layout With Under-Array Sense Amplifier Routing
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Solution Overview
Problem
Current semiconductor technologies face challenges in increasing storage capability within a given area and designing an area-efficient memory driving circuit for memory arrays.
Innovation Solution
The memory integrated circuit design places the driving circuit below the memory arrays, allowing for reduced spacing between adjacent arrays, increased storage capacity, and flexible routing schemes that connect bit lines to sense amplifiers, enabling efficient read operations and scaling down memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the driving circuit is placed between memory arrays, then the memory arrays can be accessed, but the spacing between adjacent memory arrays increases, reducing storage capability per area
Solution Approach 1:
The patent applies dimensionality change by moving the driving circuit from a lateral position (between memory arrays in the plane) to a vertical position (below the memory arrays in the third dimension). This allows the bit lines to extend vertically through via structures, enabling the driving circuit to be placed in the z-direction while maintaining electrical connectivity, thus reducing lateral spacing between memory arrays and increasing storage density.
Solution Approach 2:
The patent implements nesting by placing the driving circuit beneath the memory arrays, with the bit lines extending vertically from the driving circuit through the memory array structure. The via structures are nested within the interlayer dielectric layers, allowing compact integration where the driving circuit is contained within the vertical footprint of the memory arrays rather than occupying additional lateral space.
2Area of stationary object
If the driving circuit is placed below memory arrays, then spacing between arrays is reduced and storage capacity increases, but routing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the bit line into multiple segments: a first bit line portion extending from the driving circuit to the first via structure, a second bit line portion extending from the first via structure to the memory array, and additional segments for subsequent arrays. This segmentation allows each portion to be optimized independently and simplifies the routing by breaking down the complex vertical-to-lateral transition into manageable segments.
Solution Approach 2:
The patent uses via structures as intermediary elements that mediate the connection between the vertically placed driving circuit and the laterally arranged memory arrays. These via structures act as transition points that convert vertical electrical connections into lateral connections, simplifying the overall routing complexity by providing standardized intermediate connection points.
3Area of stationary object
If sense amplifiers are integrated within memory array boundaries, then area efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies universality by designing the via structures to serve multiple functions: they provide electrical connection between bit line portions, act as alignment reference points for sense amplifier placement, and enable the transition from vertical to lateral routing. This multi-functionality reduces the need for separate dedicated structures, thereby improving area efficiency while maintaining manufacturability through standardized features.
Data Source
AI summary
A memory integrated circuit is provided. The memory integrated circuit includes a first memory array, a second memory array and a driving circuit. The first and second memory arrays are laterally spaced apart, and respectively include: memory cells, each including an access transistor and a storage capacitor coupled to the access transistor; bit lines, respectively coupled to a row of the memory cells; and word lines, respectively coupled to a column of the memory cells. The driving circuit is disposed below the first and second memory arrays, and includes sense amplifiers. Each of the bit lines in the first memory array and one of the bit lines in the second memory array are routed to input lines of one of the sense amplifiers.