Memory Array Sense Amplifier Layout With Underground Bitlines
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Solution Overview
Problem
Conventional integrated circuits face challenges in reducing area, power consumption, and noise due to the need for large source or drain diffusion areas and limitations in shrinking DRAM dimensions caused by metal wire interconnections, which hinder further scaling and performance improvement.
Innovation Solution
The implementation of a memory array circuit with underground interconnection lines embedded in the silicon substrate, where connection lines are isolated from the substrate, allowing for more compact and efficient signal transmission between transistors and interconnects, reducing the need for surface-level metal wires and minimizing area penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metal wires and contact holes are used to connect transistors, then signal transfer is enabled, but area increases due to large source or drain diffusion areas required for alignment tolerance
Solution Approach 1:
The patent moves the bitline from the surface level to an underground position below the transistor diffusion regions. This dimensional change allows the bitline to pass through or beneath the diffusion areas without requiring lateral alignment tolerance, thereby reducing the diffusion area while maintaining electrical connection.
Solution Approach 2:
The patent introduces an intermediary structure (the underground bitline positioned between the surface and the substrate bottom) that connects the source/drain regions to the metal interconnect layer without requiring direct surface contact holes. This intermediary approach eliminates the alignment tolerance requirement between contact holes and diffusion regions.
2Productivity
If metal wires are disposed above the silicon substrate, then connection is achieved, but DRAM dimension shrinkability is limited
Solution Approach 1:
The patent relocates the bitline to an underground dimension below the surface-level metal interconnect structure. This enables independent optimization of surface metal pitch and underground bitline positioning, removing the constraint that metal wire pitch limits DRAM cell shrinkage and allowing further dimension reduction.
3Use of energy by moving object
If conventional surface-level interconnections are used, then area is occupied by metal wires and contact holes, but this increases capacitance and power consumption
Solution Approach 1:
The underground bitline position reduces the overlapping area between interconnect structures and active transistor regions, thereby reducing parasitic capacitance. This dimensional relocation also shortens the effective interconnection length, reducing RC delay and power consumption.
Data Source
AI summary
A memory array circuit includes a semiconductor substrate, a bitline, a complementary bitline, and a bitline sense amplifier circuit, wherein the bitline sense amplifier circuit includes a first plurality of transistors and a first set of connection lines. The semiconductor substrate has an original surface. The bitline sense amplifier circuit is connected to the bitline and the complementary bitline. Each transistor includes a gate node, a first conductive node, and a second conductive node. The first set of connection lines connects the first conductive nodes of the first plurality of transistors to the bitline and the complementary bitline. The first set of connection lines are under the original surface of the semiconductor substrate.