3D Memory Array Via Isolation for Direct Tier Coupling
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Solution Overview
Problem
Current memory array technologies face challenges in efficiently forming vertically-stacked memory cells with direct electrical coupling to conductor tiers without alternative processing, and in achieving reliable electrical isolation between memory blocks.
Innovation Solution
The method involves forming a stack of vertically-alternating insulative and conductive tiers, with channel openings etched through to directly couple channel material to the conductor tier, and using conductive vias and insulative material to create a covered void-space around the vias for electrical isolation, allowing for efficient formation of memory cells with charge-blocking and storage regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If vertically-stacked memory cells are formed with direct electrical coupling to conductor tiers, then manufacturing complexity is reduced, but electrical isolation between memory blocks becomes difficult to achieve
Solution Approach 1:
An insulating material layer is introduced as an intermediary between adjacent memory blocks at the conductor tier level. This insulating layer is formed laterally between conductive vias of adjacent blocks, providing electrical isolation without requiring alternative processing for the vertically-stacked memory cell structure. The insulating material acts as a mediator that prevents electrical interference between blocks while maintaining the simplified direct-coupling architecture.
2Reliability
If conventional memory array formation methods are used, then electrical isolation between memory blocks is achieved, but additional alternative processing is required that reduces productivity
Solution Approach 1:
The formation of the insulating material layer laterally between conductive vias is merged with the existing memory array fabrication process flow. This insulating layer is formed as part of the standard processing sequence rather than as a separate alternative processing step. By combining the electrical isolation function into the regular manufacturing flow, productivity is maintained while reliable electrical isolation between memory blocks is achieved.
3Manufacturing precision
If channel material is directly coupled to conductor tier through etched openings, then manufacturing precision is improved, but charge-blocking and storage regions require additional processing
Solution Approach 1:
The insulating material layer is formed in advance during the fabrication process, before the charge-blocking and storage regions are created. This preliminary formation of the insulating barrier simplifies subsequent processing by pre-establishing the electrical isolation framework. The charge-blocking and storage regions can then be formed using standard processing techniques without requiring complex alternative methods, as the insulating infrastructure is already in place.
Data Source
AI summary
A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias. Insulative material formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.