Memory Array Dielectric Layout for Void-Safe Top Contacts

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Solution Overview

Problem

Current memory array structures in NAND flash memory devices face challenges in optimizing the fabrication process, particularly in forming top contacts over data lines without breaching adjacent voids, which can lead to inefficiencies and reliability issues.

Innovation Solution

The proposed solution involves forming a solid dielectric material between data lines to prevent void formation and ensuring that top contacts are adequately sized and positioned to avoid breaching these voids, thereby enhancing contact integrity and reducing fabrication complexities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If top contacts are formed over data lines in conventional NAND flash memory fabrication, then electrical connection is achieved, but adjacent voids may be breached leading to reliability issues

Engineering Contradiction:
Improvecontact integrityVSAvoidvoid breach
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A solid dielectric material is formed between data lines before top contact formation to preemptively prevent void creation. This preliminary structural preparation ensures that when top contacts are subsequently formed, there is already a barrier in place to prevent void breaches, thereby improving contact integrity without compromising reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The solid dielectric material acts as an intermediary layer between data lines and top contacts. This intermediate structure serves as a protective barrier that prevents direct interaction between the top contact formation process and potential voids, thereby eliminating the harmful effect of void breaches while maintaining electrical connectivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If solid dielectric material is formed between data lines to prevent void formation, then contact integrity is improved, but fabrication process complexity increases

Engineering Contradiction:
Improvecontact integrityVSAvoidfabrication process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The fabrication process utilizes parameter changes in the dielectric material properties, specifically transitioning from a void-containing structure to a solid dielectric structure between data lines. This parameter change (from void to solid material) is achieved through controlled deposition or filling processes that modify the physical state and density of the material in the inter-data-line region, thereby preventing void formation while maintaining process feasibility.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If top contacts are adequately sized and positioned to avoid void breaches, then reliability is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecontact integrityVSAvoidcontact positioning
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The solid dielectric material is formed between data lines before top contact patterning and formation. This preliminary structural preparation establishes a protective barrier that reduces the precision requirements for subsequent top contact alignment, as the dielectric layer provides a buffer that prevents void breaches even with moderate positioning variations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240071966A1Memory array structures and methods of their fabrication
Publication Date: 2024.02.29 MICRON TECHNOLOGY INC
  • US20240071966A1 patent drawing
  • US20240071966A1 patent drawing
  • US20240071966A1 patent drawing

AI summary

Memory array structures might include a first data line selectively connected to a first plurality of memory cells, a second data line selectively connected to a second plurality of memory cells, a solid first dielectric extending between a first portion of the first data line and a first portion of the second data line, a second dielectric containing a void extending between a second portion of the first data line and a second portion of the second data line, and a top contact overlying and in contact with the first portion of the first data line.