Memory Array Voltage Compensation for Programming and Erase Variations
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Solution Overview
Problem
Existing memory devices with certain architectures face challenges in achieving consistent and efficient programming and erasing operations across different memory blocks, due to variations in programming and erasing efficiencies.
Innovation Solution
A memory device architecture that includes a CMOS wafer with control circuitry configured to output different initial programming voltages and unique erase voltages to array wafers, optimizing the voltages for each array wafer based on its specific programming and erasing efficiencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single initial programming voltage is applied to all array wafers, then device complexity is reduced, but programming efficiency and reliability deteriorate due to variations in programming efficiencies across different array wafers
Solution Approach 1:
The patent applies different initial programming voltages to different array wafers based on their specific programming efficiency characteristics. The control circuitry identifies which array wafer has higher programming efficiency and applies a lower initial voltage to it, while applying a higher initial voltage to array wafers with lower programming efficiency. This local differentiation ensures each array wafer receives optimized voltage treatment for its specific performance characteristics.
Solution Approach 2:
The patent dynamically adjusts the initial programming voltage parameter based on the programming efficiency of different array wafers. By changing the voltage parameter according to measured or characterized programming efficiencies, the system optimizes programming operations for each array wafer, improving overall reliability and performance consistency.
2Reliability
If different initial programming voltages are applied to different array wafers, then programming efficiency and reliability improve, but device complexity increases
Solution Approach 1:
The patent segments the voltage control into different groups corresponding to different array wafers. The control circuitry divides array wafers into at least two groups based on their programming efficiency characteristics and applies different initial programming voltages to each group. This segmentation allows manageable complexity while achieving optimized performance for each segment.
Solution Approach 2:
The patent implements a feedback mechanism where the control circuitry monitors or characterizes the programming efficiency of different array wafers and uses this information to determine appropriate initial programming voltages. This feedback loop enables automatic adaptation to the specific performance characteristics of each array wafer, reducing the burden on external configuration and simplifying overall system control.
3Productivity
If higher initial programming voltage is applied to array wafers with lower programming efficiency, then programming speed improves, but energy consumption increases
Solution Approach 1:
The patent applies higher initial programming voltages only to specific array wafers that have been identified as having lower programming efficiency, rather than uniformly increasing voltage across all array wafers. This localized approach ensures that energy consumption is increased only where necessary to achieve acceptable programming speeds, optimizing the balance between productivity and energy usage.
Data Source
AI summary
The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.