Memory Array Voltage Control for Read Margin Errors

Solution Overview

Problem

Integrated circuits face challenges in reducing power consumption while maintaining reliable operation, as lowering power supply voltage increases susceptibility to soft errors and process variations, and boosting/decreasing voltage for read/write operations can lead to increased power consumption.

Innovation Solution

Implementing read and write assist bits to dynamically adjust power supply voltage for memory cells with inadequate margins, using separate storage for assist bits and threshold voltages to minimize power consumption and latency, and utilizing a voltage regulator with multiplexers to manage power supply voltages efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If power supply voltage is lowered to reduce power consumption, then power consumption decreases, but read margins deteriorate and susceptibility to soft errors increases

Engineering Contradiction:

Improvepower consumptionVSAvoidread margins

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies local quality by providing different power supply voltages to different portions of the memory array based on their specific needs. The memory array is divided into multiple portions, and each portion can receive a voltage level selected from first, second, or third voltage levels according to its read margin requirements, allowing targeted voltage boosting only where needed rather than uniformly across the entire array.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements dynamics by making the power supply voltage configurable and adjustable based on operating conditions. The system can dynamically select between multiple voltage levels (first, second, and third voltage levels) for different portions of the memory array, enabling adaptive voltage control that responds to changing read margin requirements while managing power consumption.

Inventive Principle:

Principle #15Dynamics

2Reliability

If power supply voltage is boosted during read operations to improve read margins, then read margins improve, but power consumption increases

Engineering Contradiction:

Improveread marginsVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies local quality by providing different power supply voltages to different portions of the memory array based on their specific needs. The memory array is divided into multiple portions, and each portion can receive a voltage level selected from first, second, or third voltage levels according to its read margin requirements, allowing targeted voltage boosting only where needed rather than uniformly across the entire array.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent applies partial action by providing voltage boosting only to specific portions of the memory array that require it, rather than boosting the entire array. The system selectively applies higher voltage levels to portions with inadequate read margins while maintaining lower voltage levels in other portions, thus achieving the necessary read margins with minimal additional power consumption.

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If power supply voltage is decreased during write operations to improve write margins, then write margins improve, but power consumption increases

Engineering Contradiction:

Improvewrite marginsVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies local quality by providing different power supply voltages to different portions of the memory array based on their specific needs. The memory array is divided into multiple portions, and each portion can receive a voltage level selected from first, second, or third voltage levels according to its read margin requirements, allowing targeted voltage control for write operations in specific regions.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS7903483B2Integrated circuit having memory with configurable read/write operations and method therefor

Publication Date: 2011.03.08 NXP USA INC

AI summary

An integrated circuit having a memory and a method for operating the memory are provided. The method for operating the memory comprises: accessing a first portion of the memory, the first portion having a first access margin; detecting an error in the first portion of the memory; changing the first access margin to a second access margin, the second access margin being different than the first access margin; determining that the error is corrected with the first portion having the second access margin; and storing an access assist bit in a first storage element, the access assist bit corresponding to the first portion, wherein the assist bit, when set, indicates that subsequent accesses to the first portion are accomplished at the second access margin.