Memory Cell Array Layout for Faster Word Line Voltage Propagation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently propagating voltage to word lines due to high wiring resistance, which degrades write and read performance, especially with the miniaturization and increased density of memory cell transistors.
Innovation Solution
Incorporating a connection region between cell regions that short-circuits select gate lines and word lines, allowing for simultaneous voltage application to both cell regions, thereby reducing wiring length and resistance, and sharing the row decoder module to improve voltage propagation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell transistors are miniaturized and density is increased, then storage capacity is improved, but wiring resistance increases and voltage propagation deteriorates
Solution Approach 1:
The memory cell array is divided into multiple cell regions (first cell region and second cell region) with connection regions positioned between them. This segmentation allows independent voltage application to different cell regions, reducing the overall wiring length and resistance while maintaining high memory cell density throughout the array.
Solution Approach 2:
Connection regions are introduced as intermediary structures between cell regions and the row decoder module. These connection regions include select gate lines and word lines that act as mediators to propagate voltage from the row decoder to memory cell transistors, effectively reducing the direct wiring length and resistance from the decoder to distant cells.
2Speed
If wiring length is reduced to decrease resistance, then voltage propagation speed is improved, but the area required for connection structures increases
Solution Approach 1:
The connection regions and select gate lines are arranged in a three-dimensional configuration with the row decoder module positioned in a lower layer and connection regions extending upward to reach cell regions in upper layers. This vertical arrangement reduces planar wiring length and resistance while efficiently utilizing the available area by transitioning from two-dimensional to three-dimensional space utilization.
3Area of stationary object
If row decoder module area is reduced, then device integration is improved, but voltage propagation capability to all cell regions deteriorates
Solution Approach 1:
The row decoder module is segmented into multiple independent decoder units, each capable of independently controlling voltage application to different cell regions. This segmentation allows a compact decoder area while maintaining comprehensive voltage propagation coverage across the entire memory cell array through distributed control.
Solution Approach 2:
The connection regions are designed with multi-functionality, serving both as voltage propagation pathways and as control structures for selective cell region activation. The select gate lines and word lines in connection regions perform multiple functions including voltage distribution, cell selection, and signal routing, thereby reducing the need for dedicated structures and minimizing overall area while maintaining propagation capability.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first cell region including a plurality of memory cells, a second cell region including a plurality of memory cells, a connection region between the first cell region and the second cell region, and a row decoder for propagating a voltage to word lines in the first and second cell regions via the connection region.