Memory Array Voltage Regulation for Leakage Reduction
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Solution Overview
Problem
Integrated circuits face challenges in reducing leakage currents during low power modes without compromising data integrity, especially as transistor leakage increases with finer geometry manufacturing processes and larger cache memories lead to more leakage paths.
Innovation Solution
An integrated circuit design that includes a memory array with a voltage regulator using N-channel transistors and a bias circuit to elevate the ground connection voltage during standby mode, utilizing dummy edge cells to manage leakage current and track variations due to process, voltage, and temperature changes, thereby reducing power consumption without affecting reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the cache memory size is increased to take advantage of finer geometry manufacturing processes, then the storage capacity is improved, but the number of leakage paths increases resulting in higher leakage current
Solution Approach 1:
The cache memory is divided into multiple banks, allowing selective activation. During idle periods, individual banks can be placed in low power mode while others remain active, reducing total leakage current without compromising overall storage capacity.
Solution Approach 2:
The patent dynamically adjusts the virtual ground voltage level based on operating conditions. During low power mode, the virtual ground voltage is elevated to a specific level that reduces leakage current while maintaining data integrity in the memory cells.
2Loss of energy
If the virtual ground terminal voltage is increased during low power mode to reduce leakage current, then power consumption is reduced, but data integrity may be compromised if the voltage is not maintained accurately
Solution Approach 1:
A feedback mechanism monitors the virtual ground voltage level and adjusts it dynamically. The system detects voltage deviations and corrects them in real-time, ensuring the virtual ground voltage remains within the optimal range for leakage reduction while maintaining data integrity.
Solution Approach 2:
The patent introduces a dedicated voltage regulation circuit as an intermediary between the power supply and the memory cells. This circuit acts as a buffer that precisely controls the virtual ground voltage, isolating the memory cells from power supply variations and ensuring stable operation during low power mode.
3Device complexity
If traditional power reduction techniques are used, then implementation simplicity is maintained, but they become ineffective as transistor leakage currents increase with finer geometry processes
Solution Approach 1:
The patent implements dynamic voltage scaling where the virtual ground voltage is adjusted in real-time based on the operational state of the memory. During active modes, the virtual ground remains at standard levels for optimal performance. During idle or low power modes, the virtual ground voltage is elevated to reduce leakage, creating a dynamic adaptation to changing conditions.
Data Source
AI summary
An integrated circuit comprises a memory array and a bias circuit. The memory array comprises a plurality of memory cells arranged in a grid of rows and columns. A first conductor is coupled to a power supply voltage terminal of each of the plurality of memory cells. A second conductor is coupled to receive a power supply voltage. The memory array also includes a plurality of dummy cells. A transistor of one or more of the plurality of dummy cells has a first current electrode coupled to the first conductor, a second current electrode coupled to the second conductor, and a control electrode. The bias circuit is coupled to the control electrode of the transistor.