3D Memory Array Wall Structure to Prevent Block Bending

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Solution Overview

Problem

Existing memory array fabrication processes face challenges with 'block-bending' during fabrication, where memory blocks can tilt or bend sideways relative to their longitudinal orientation, affecting the integrity and reliability of the memory array.

Innovation Solution

The proposed solution involves forming a memory array with laterally-spaced memory blocks, each comprising a vertical stack of alternating insulative and conductive tiers. This configuration includes the formation of elevationally-extending walls that encircle islands between memory blocks, and stair-step structures with specific orientations and configurations to prevent block-bending and ensure structural integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If memory blocks are formed in conventional fabrication processes, then memory array production is achieved, but block-bending occurs causing memory blocks to tilt or bend sideways relative to their longitudinal orientation

Engineering Contradiction:
Improveblock orientationVSAvoidmemory array integrity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The fabrication process is divided into distinct stages: forming sacrificial blocks, creating trenches, depositing memory block materials, and removing sacrificial blocks. This segmentation allows precise control at each stage to prevent block-bending while maintaining manufacturing efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Sacrificial blocks are formed and positioned before the memory block materials are deposited. These sacrificial structures serve as temporary supports and alignment references during fabrication, ensuring that memory blocks are deposited in the correct orientation and position before the sacrificial blocks are removed.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If memory blocks are laterally-spaced with elevationally-extending walls and stair-step structures, then block-bending is prevented and structural integrity is enhanced, but device complexity increases

Engineering Contradiction:
Improvememory array integrityVSAvoidfabrication structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Elevationally-extending walls are formed between laterally-spaced memory blocks to act as intermediary structures that prevent lateral movement and block-bending. These walls provide mechanical support and maintain the longitudinal orientation of memory blocks without requiring complex active control mechanisms.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Instead of attempting to control block orientation solely in the lateral plane, the invention extends support structures vertically (elevationally) to create stair-step structures. This dimensional approach provides robust mechanical constraints against block-bending while maintaining a relatively simple fabrication process.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12213317B2Memory arrays and methods used in forming a memory array comprising strings of memory cells
Publication Date: 2025.01.28 MICRON TECHNOLOGY INC
  • US12213317B2 patent drawing
  • US12213317B2 patent drawing
  • US12213317B2 patent drawing

AI summary

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.