3D Memory Cell Array Layout to Reduce Word Line Coupling
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Solution Overview
Problem
As semiconductor memory devices shrink, the reduced pitch between memory cells leads to increased coupling effects between word lines, resulting in reduced word line speed and integrated circuit performance.
Innovation Solution
The memory device configuration includes word lines on odd-numbered tiers oriented differently from those on even-numbered tiers, with an angular offset, which reduces cell-to-cell spacing and minimizes coupling effects between adjacent tiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the pitch between memory cells is reduced to shrink device size, then device miniaturization is achieved, but coupling effects between word lines increase
Solution Approach 1:
The patent applies asymmetry by orienting word lines on odd-numbered tiers at a first angle (e.g., 0 degrees) and word lines on even-numbered tiers at a second angle (e.g., 30-60 degrees) relative to a reference direction. This asymmetric angular arrangement breaks the direct alignment between stacked word lines, thereby reducing capacitive coupling effects while maintaining reduced pitch for device miniaturization
2Productivity
If word line spacing is reduced to increase cell density, then integration density is improved, but word line speed decreases due to increased coupling
Solution Approach 1:
By implementing asymmetric angular offsets between word lines on adjacent tiers (odd tiers at angle θ1, even tiers at angle θ2 where θ1 ≠ θ2), the patent reduces parasitic capacitive coupling between closely spaced word lines. This enables maintained word line speed despite reduced spacing by minimizing the harmful electric field interaction between adjacent tiers
Data Source
AI summary
A memory device includes transistors and a memory cell array disposed over and electrically coupled to the transistors. The memory cell array includes word lines, bit line columns, and data storage layers interposed between the word lines and the bit line columns. A first portion of the word lines on odd-numbered tiers of the memory cell array is oriented in a first direction, and a second portion of the word lines on even-numbered tiers of the memory cell array is oriented in a second direction that is angularly offset from the first direction. The bit line columns pass through the odd-numbered tiers and the even-numbered tiers, and each of the bit line columns is encircled by one of the data storage layers. A semiconductor die and a manufacturing method of a semiconductor structure are also provided.