Semiconductor Memory Arrays With Shared Row Decoder Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently integrating and optimizing the electrical connections between multiple memory cell arrays and a circuit chip, particularly in three-dimensional stacked NAND flash memory configurations, which can lead to inefficiencies in data access and operation.
Innovation Solution
The semiconductor memory device employs a configuration where multiple array chips and a circuit chip are bonded, with each array chip having distinct electrical connections to a shared row decoder, while maintaining independent connections for select gate lines, thereby optimizing data access and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory cell arrays are integrated in a three-dimensional stacked configuration, then storage capacity is improved, but connection efficiency and data access performance deteriorate
Solution Approach 1:
The patent divides the memory system into multiple array chips (first memory cell array, second memory cell array, etc.) stacked in three dimensions, with each array chip having independent electrical connections to the circuit chip. This segmentation allows parallel access to different memory arrays, improving data access efficiency while maintaining high storage capacity.
Solution Approach 2:
The circuit chip serves as a universal control unit that can simultaneously control multiple memory cell arrays through shared decoders (row decoder, column decoder) and control circuits. This multi-functionality enables efficient data access across all stacked arrays without requiring separate control chips for each array.
2Device complexity
If multiple array chips are connected to a shared row decoder, then device complexity is reduced, but connection efficiency may worsen
Solution Approach 1:
The patent merges multiple row decoders into a single shared row decoder that can simultaneously decode addresses for multiple memory cell arrays. Similarly, control circuits are combined to manage all arrays. This merging reduces overall device complexity while maintaining connection efficiency through parallel processing capabilities of the shared decoders.
Data Source
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AI summary
According to an embodiment, a semiconductor memory device includes a first memory cell array, a second memory cell array, and a row decoder. The first memory cell array includes a first select transistor, a first memory cell, a second select transistor, a first word line, a first select gate line, and a second select gate line. The second memory cell array includes, a third select transistor, a second memory cell, a fourth select transistor, a second word line, a third select gate line, a fourth select gate line. The first word line and the second word line are commonly coupled to the row decoder. The first select gate line, the second select gate line, the third select gate line, and the fourth select gate line are separately coupled to the row decoder.