Integrated Memory Assemblies with Localized Semiconductor Doping
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Solution Overview
Problem
Current integrated memory fabrication processes face challenges in developing common processing steps for both memory-array-regions and peripheral regions of semiconductor dies, which hinders the integration of efficient bitline contacts and charge-storage devices.
Innovation Solution
The method involves forming integrated assemblies with bitline-contact-structures spaced from charge-storage-device-contact-structures by insulative regions, using semiconductor material with varying dopant configurations – nonconductive in memory-array-regions and conductive in peripheral regions, allowing for shared processing steps across both areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate processing steps are used for memory-array-region and peripheral region, then manufacturing precision of individual regions is improved, but device complexity and processing time increase
Solution Approach 1:
The patent combines the fabrication processes for memory-array-region and peripheral region into a single integrated process sequence. Common processing steps including forming insulative regions, depositing semiconductor materials, and creating contact structures are performed simultaneously across both regions, eliminating the need for separate processing sequences while maintaining manufacturing precision through unified process control
Solution Approach 2:
The patent employs universal processing steps that serve multiple functions across different regions. For example, the same insulative region formation process serves both memory-array isolation and peripheral circuit separation needs, and the same semiconductor material deposition creates both nonconductive insulative regions and conductive contact structures depending on location and doping application
2Manufacturing precision
If separate processing steps are used for memory-array-region and peripheral region, then manufacturing precision of individual regions is improved, but productivity decreases
Solution Approach 1:
The patent merges the fabrication processes for memory-array-region and peripheral region into a single integrated process sequence. Common processing steps including forming insulative regions, depositing semiconductor materials, and creating contact structures are performed simultaneously across both regions, eliminating the need for separate processing sequences while maintaining manufacturing precision through unified process control
Solution Approach 2:
The patent performs preliminary actions by forming insulative regions and preparing semiconductor material layers across the entire die before region-specific differentiation. This preliminary structuring enables subsequent selective doping and contact formation to proceed efficiently without requiring separate preparatory steps for each region
3Reliability
If nonconductive semiconductor material is used in memory-array-region, then reliability of charge-storage devices is improved, but device complexity increases due to varying dopant configurations
Solution Approach 1:
The patent applies local quality by using nonconductive (undoped or lightly-doped) semiconductor material specifically in the memory-array-region insulative regions to ensure charge-storage device reliability, while using conductively-doped semiconductor material in peripheral regions for contact structures. The doping concentration and electrical properties are locally optimized for each region's functional requirements without requiring complex global doping schemes
Solution Approach 2:
The patent changes the dopant concentration parameter selectively across different regions and structures. Insulative regions in the memory-array use low or zero dopant concentrations to maintain nonconductive properties, while peripheral contact structures use high dopant concentrations for conductivity. This parameter variation is achieved through selective doping processes applied at different stages of fabrication
4Ease of operation
If conductively-doped semiconductor material is used in peripheral region, then ease of operation for bitline contacts is improved, but manufacturing precision control becomes more difficult
Solution Approach 1:
The patent performs preliminary actions by forming insulative regions and preparing semiconductor material layers across the entire die before region-specific differentiation. This preliminary structuring enables subsequent selective doping and contact formation to proceed efficiently without requiring separate preparatory steps for each region
Solution Approach 2:
The patent applies local quality by using nonconductive (undoped or lightly-doped) semiconductor material specifically in the memory-array-region insulative regions to ensure charge-storage device reliability, while using conductively-doped semiconductor material in peripheral regions for contact structures. The doping concentration and electrical properties are locally optimized for each region's functional requirements without requiring complex global doping schemes
Data Source
AI summary
Some embodiments include an integrated assembly having a paired-memory-cell-region within a memory-array-region. The paired-memory-cell-region includes a bitline-contact-structure between a first charge-storage-device-contact-structure and a second charge-storage-device-contact-structure. A first insulative region is between the bitline-contact-structure and the first charge-storage-device-contact-structure. A second insulative region is between the bitline-contact-structure and the second charge-storage-device-contact-structure. The first and second insulative regions both include a first semiconductor material which is in a nonconductive configuration. A transistor gate is over a peripheral region proximate the memory-array-region. The transistor gate has a second semiconductor material which is a same semiconductor composition and thickness as the first semiconductor material, but which is in a conductive configuration. Some embodiments include methods of forming integrated assemblies.