Semiconductor Memory Device Asymmetric Conductive Layer Lengths
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Solution Overview
Problem
In cross-point semiconductor memory devices, as the number of memory cells increases, the lengths of bit lines and word lines also increase, leading to non-constant voltages applied to memory cells due to voltage reduction, resulting in voltage fluctuations that affect operation stability.
Innovation Solution
The semiconductor memory device design includes conductive layers and memory cells arranged in a specific configuration where the length of the first-layer second conductive layer is shorter than the second-layer second conductive layer, reducing voltage fluctuations and improving operation stability by maintaining more equalized voltages across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased, then the storage capacity is improved, but the lengths of bit lines and word lines increase causing voltage fluctuations and operation instability
Solution Approach 1:
The memory device is divided into multiple stacks arranged in a three-dimensional cross-point configuration. Each stack contains multiple memory cells separated by intermediate conductive layers, allowing independent voltage control for each memory cell. This segmentation enables increased memory cell density without proportionally increasing bit line and word line lengths, thereby maintaining operation stability while improving storage capacity.
2Quantity of substance
If the lengths of bit lines and word lines are increased to accommodate more memory cells, then the storage capacity is improved, but voltage reduction and fluctuations occur affecting operation stability
Solution Approach 1:
The patent transitions from a two-dimensional memory layout to a three-dimensional cross-point architecture with multiple stacked layers. Memory cells are arranged in vertical stacks with intermediate conductive layers positioned between upper and lower memory cells. This dimensional change allows storage capacity to increase vertically rather than horizontally, keeping bit line and word line lengths relatively constant while improving voltage stability and operation reliability.
3Reliability
If the first-layer second conductive layer length is made shorter than the second-layer second conductive layer length, then voltage fluctuations are reduced and operation stability is improved, but the device complexity increases
Solution Approach 1:
The patent implements asymmetric conductive layer lengths where the first-layer second conductive layer has a different length than the second-layer second conductive layer. This local quality variation is strategically applied to compensate for voltage drops in specific regions of the memory device. By optimizing the length of individual conductive layers based on their position and electrical characteristics, the patent reduces voltage fluctuations and improves operation stability without requiring complete redesign of the entire device structure.
Data Source
AI summary
According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.