Memory-Attached Computing Resource for NoC Power Efficiency
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Solution Overview
Problem
Conventional computer systems face inefficiencies due to the CPU handling memory access tasks, leading to high power consumption and poor scalability, as processing engines spend time on memory transactions and complex programming is required to minimize cross-node communication.
Innovation Solution
A memory-attached computing resource is introduced, attached to memory via an external memory interface, which assists processing engines by handling memory access tasks, allowing them to focus on computation and reducing power consumption by offloading memory transactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the CPU handles memory access tasks, then the system can maintain a simple architecture, but power consumption increases and scalability deteriorates
Solution Approach 1:
The patent divides the memory access functionality into separate memory access hardware units that are dedicated to handling memory transactions. This segments the CPU's workload, allowing it to focus on computation while specialized hardware handles memory access, thereby reducing power consumption without significantly increasing overall system complexity.
Solution Approach 2:
The patent introduces memory access hardware as an intermediary component between the CPU and external memory. This mediator handles all memory access tasks, freeing the CPU from power-intensive memory management operations while maintaining a relatively simple system architecture through standardized interfaces.
2Device complexity
If the CPU handles memory access tasks, then the system architecture remains simple, but scalability worsens due to processing engines spending time on memory transactions
Solution Approach 1:
By segmenting memory access operations into dedicated hardware units, the patent enables multiple processing engines to access memory in parallel without contending for CPU resources. This improves scalability while keeping the architecture simple through modular, independent memory access units.
Solution Approach 2:
The memory access hardware operates autonomously to service memory requests from multiple processing engines simultaneously. This self-service capability allows the system to scale to more processing engines without proportionally increasing CPU involvement in memory management, thereby improving productivity and scalability.
3Ease of operation
If processing engines handle their own memory transactions, then autonomy is maintained, but latency increases due to time spent on memory access
Solution Approach 1:
The patent introduces dedicated memory access hardware as an intermediary that processing engines can autonomously utilize. This maintains processing engine autonomy while dramatically reducing memory transaction latency through specialized hardware optimization, as engines issue requests to the intermediary without direct CPU involvement.
Solution Approach 2:
The patent replaces the software-based memory management approach (where the CPU would handle memory transactions) with hardware-based memory access units. This substitution reduces latency through direct hardware access while maintaining processing engine autonomy through standardized hardware interfaces.
4Use of energy by moving object
If specialized hardware is added to assist with memory access, then power efficiency improves, but device complexity increases
Solution Approach 1:
The patent applies local quality by implementing specialized memory access hardware units with specific functions optimized for their particular tasks. Each unit is designed with the exact capabilities needed for its role, improving power efficiency through targeted optimization while keeping overall complexity manageable through functional specialization.
Solution Approach 2:
The memory access hardware units are designed with universal interfaces and capabilities that allow them to service multiple processing engines and handle various types of memory operations. This multi-functionality improves power efficiency across the entire system while avoiding the complexity of having separate dedicated hardware for each processing engine.
Data Source
AI summary
A computing system includes a plurality of computing resources that communicate with each other using network on a chip architecture. One of the plurality of computing resources is attached to memory external to the computing system through an external memory interface. The memory-attached computing resource is configured to read data from the memory and modify the read data prior to either writing the modified data back to the memory, or transmitting the modified data to one or more other of the computing resources, or both.