Memory Device Auxiliary Circuit Voltage Control

A write buffer circuit is introduced as an intermediary component between the word line driver and the memory cell array. The write buffer circuit includes a first write buffer and a second write buffer that are coupled to the same word line, allowing differential writing operations. This intermediary structure enables precise control of the write operation timing and voltage levels, reducing the harmful half-select-disturb effect while maintaining fast write speed through buffered signal driving capability.

The invention employs dynamic control of the write operation by using two separate write buffers that can be independently activated. The first write buffer writes to memory cells in a first column while the second write buffer writes to memory cells in a second column. This dynamic switching and differential operation allows the system to maintain large pass transistor sizes for fast writing while precisely controlling when each cell is affected by the write voltage, thereby minimizing half-select disturbance.

The write buffer circuit acts as a mediator that provides strong driving capability to the word line during write operations. This allows the use of smaller pass transistors (reducing half-select disturb) while the buffer ensures sufficient write voltage and current are delivered to overcome the smaller transistor's reduced drive strength, thereby maintaining adequate write margin and reliability.

By using dynamic differential writing through two write buffers, the system can concentrate the write effort on selected cells while minimizing disturbance to unselected cells. The dynamic control allows small pass transistors to be used without sacrificing write margin, as the buffered write operation provides precise voltage control and timing that compensates for the smaller transistor size.