Memory-Aware Circuit Region Partitioning for EDA Routing
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Solution Overview
Problem
The existing electronic design automation (EDA) processes for VLSI digital design face challenges in efficiently managing memory requirements for routing tasks, particularly in Extreme Ultraviolet (EUV) technology, leading to increased runtime and memory demands that often exceed available resources, necessitating large dedicated machines and prolonged waiting times.
Innovation Solution
The implementation of system memory-aware circuit region partitioning techniques, which involve running a sweep line algorithm on active and inactive metal shapes to dynamically compute memory requirements and partition the design into smaller sections, allowing routing jobs to be processed in smaller computer systems without exceeding available memory, thereby optimizing memory usage and reducing runtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional EDA routing processes are used on large VLSI designs, then routing completeness can be achieved, but memory requirements exceed available system memory resources
Solution Approach 1:
The patent divides the large VLSI circuit design into multiple smaller partitions or regions. Each partition is routed separately using the sweep line algorithm, which reduces the memory requirement for each individual routing operation. The partitions are created by dividing the design space into manageable chunks that can fit within available system memory, allowing complete routing to be achieved through iterative processing of each partition.
2Reliability
If conventional EDA routing processes are used on large VLSI designs, then all connections can be established, but runtime becomes excessively long
Solution Approach 1:
By segmenting the design into partitions, the total runtime is reduced because each partition can be processed independently and more efficiently. The sweep line algorithm processes each partition separately, avoiding the need to load and process the entire large design at once, which significantly reduces computational overhead and runtime.
Solution Approach 2:
The patent performs preliminary actions by first dividing the design into partitions and pre-processing metadata for each partition before executing the main routing operation. This preliminary partitioning and metadata preparation enables more efficient routing execution by organizing the data in a way that optimizes memory access patterns and reduces computational complexity during the actual routing process.
3Reliability
If available system memory is exceeded during routing, then routing cannot be completed, but reducing design detail loses information needed for valid routing
Solution Approach 1:
Segmentation allows the complete design to be processed without losing information by dividing it into partitions that each fit within memory constraints. Each partition retains all necessary design details and connectivity information needed for valid routing, while the segmentation itself enables the process to complete successfully by managing memory usage within available resources.
Data Source
AI summary
To increase the efficiency of an electronic design automation (EDA) process, for a putative integrated circuit design for which computerized routing is to be carried out within an EDA program, run a sweep line algorithm selectively on active metal shapes in said putative design for different layers, to determine a total number of said active metal shapes, and compute a memory requirement for computerized routing on said active shapes based on said total number of said active shapes. For said putative design, compute a memory requirement for computerized routing on inactive metal shapes based on a total number of said inactive shapes; partition said putative design into a plurality of partitions, based on said memory requirement for computerized routing on said active and inactive shapes, such that an available system memory is not exceeded. Separately run a routing job on each of said plurality of partitions.