Semiconductor Memory Back-Bias Ripple Noise Reduction
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Solution Overview
Problem
Semiconductor memory devices, such as DRAM, face challenges in reducing both junction leakage current and sub-threshold current, as reducing one type of current increases the other, leading to ripple noise in back-bias voltage, which degrades refresh properties and causes errors.
Innovation Solution
A semiconductor memory device with a word line driving circuit and delay logic circuit that enables a sub-word line connected to a selected memory cell to a higher voltage and disables a non-selected memory cell to a ground and negative voltage, controlling the charge transition points to minimize ripple noise, using a combination of PMOS and NMOS transistors and NAND gates to manage voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If negative voltage is applied to non-selected word lines to reduce leakage current, then leakage current is reduced, but ripple noise in back-bias voltage is generated
Solution Approach 1:
The patent introduces a ripple noise reduction circuit as an intermediary component that decouples the negative bias voltage application from the back-bias voltage supply. This circuit includes a first capacitor connected between the negative bias voltage line and ground, and a second capacitor connected between the back-bias voltage line and ground. The capacitors filter out ripple noise while maintaining the negative bias effect, thus resolving the contradiction between leakage current reduction and ripple noise generation
Data Source
AI summary
A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first voltage, and disables the sub-word line of a non-selected memory cell to a second voltage and a third voltage, in response to a sub-word line enable signal, a first word line driving signal, and a second word line driving signal. The delay logic circuit controls the semiconductor memory device so that an amount of charge of the sub-word line that is introduced to the third voltage is greater than an amount of charge of the sub-word line that is introduced to the second voltage by changing a transition point of time of the sub-word line enable signal with respect to a transition point of time of the first word line driving signal, during the disabling of the sub-word line.