Memory Back-Bias Voltage Feasibility Testing
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Solution Overview
Problem
Semiconductor devices with embedded memory face challenges in achieving optimal power reduction and performance enhancement due to voltage-sensitive functional failures in SRAM memories, which are exacerbated by local and global bitcell variations and design margins needed to cover device uncertainties and aging effects, leading to increased system complexity and cost.
Innovation Solution
A method and semiconductor device that utilize a first and second memory unit with different back bias voltages for writing and reading data, allowing for the determination of a feasible operating condition with different supply voltage and frequency, enabling the memory device to transition to a new operating condition based on data comparison and validation, thereby emulating the impact of supply voltage and frequency changes without actual voltage or frequency adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If supply voltage is reduced for low-power operation, then power consumption is reduced, but functional failures occur in memory operations
Solution Approach 1:
The patent applies parameter changes by adjusting the back-bias voltage of the memory cell to compensate for reduced supply voltage. By dynamically changing the back-bias voltage parameter, the memory maintains functional reliability even when operating at lower supply voltages for power savings.
Solution Approach 2:
The patent uses preliminary action by performing feasibility testing before actual low-power operation. The system tests whether the memory can operate reliably at the intended lower voltage by writing test patterns and reading them back, then adjusts back-bias voltage accordingly before entering the low-power mode.
2Speed
If supply voltage is increased for high performance operation, then operating speed is improved, but power consumption increases
Solution Approach 1:
The patent applies parameter changes by using back-bias voltage adjustment to achieve higher operating speeds without proportionally increasing supply voltage. By optimizing the back-bias voltage parameter, the memory can operate faster while consuming less power than conventional approaches.
Solution Approach 2:
The patent implements dynamics by dynamically adjusting the back-bias voltage based on operating conditions. The system can switch between different back-bias voltage levels to optimize for either speed or power consumption depending on the current operational requirements.
3Reliability
If design margins are increased to cover device variations and aging effects, then reliability is improved, but system complexity and cost increase
Solution Approach 1:
The patent applies parameter changes by using back-bias voltage adjustment to compensate for device variations and aging effects. Instead of increasing design margins, the system dynamically adjusts the back-bias voltage parameter to maintain reliability, thereby avoiding increased system complexity.
Solution Approach 2:
The patent implements self-service by enabling the memory system to self-adjust and compensate for its own variations and aging. The feasibility testing and back-bias voltage adjustment mechanism allows the system to maintain reliability autonomously without requiring external calibration or increased design complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for predictable memory operation condition changes, reducing the risk of functional failures and optimizing power consumption and performance by emulating lower supply voltage or higher frequency operations, thereby minimizing performance penalties and power consumption while maintaining reliability.
Implementation Method 1
a first back bias voltage of the first memory unit is at a first voltage value and a second back bias voltage of the second memory unit is at a second voltage value different than the first voltage value
Data Source
AI summary
A memory device having at least one output predicting a feasibility of whether the memory device will work properly at a different operating condition including a different supply voltage and/or a different operating frequency than the current supply voltage and/or the current operating frequency. A semiconductor device (e.g. a SoC chip) provides a test to either validate or invalidate the feasibility for the memory device to enter such a different operating condition based on read and write operations of the memory device in normal access cycles. The memory device is partitioned with at least a first memory unit and a second memory unit, which can be coupled to different back-bias voltages. This operating condition predicting function can be enabled or disabled by the semiconductor device in real time operation depending on the feasibility test results.