Master-Slave Memory Back Channel Command Sharing

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Solution Overview

Problem

Current semiconductor memory devices lack an efficient method for inter-memory command and information sharing, leading to suboptimal performance and coordination between master and slave memory devices.

Innovation Solution

A memory system with a master memory device and slave memory devices is implemented, utilizing a back channel bus for internal command and information transmission, allowing synchronized operations and data sharing between devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a memory system uses multiple memory devices coupled through command/address channel to memory controller, then memory capacity and bandwidth are increased, but coordination and synchronization between master and slave memory devices become complex and inefficient

Engineering Contradiction:
Improvememory bandwidthVSAvoidcoordination complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the command channel functionality by introducing a back-channel that divides command transmission into two paths: a front-channel from memory controller to master memory device, and a back-channel from master memory device to slave memory devices. This segmentation allows independent optimization of each channel, reducing coordination complexity while maintaining high bandwidth.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The master memory device acts as an intermediary between the memory controller and slave memory devices. It receives commands from the controller via the front-channel, processes them, and generates appropriate commands for slave devices through the back-channel. This intermediary role simplifies the overall system architecture by centralizing coordination logic in the master device.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If memory devices communicate only through memory controller, then system control is simplified, but inter-memory command and information sharing efficiency is reduced

Engineering Contradiction:
Improvesystem controlVSAvoidinter-memory sharing efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent adds a new communication dimension by introducing the back-channel that enables direct master-to-slave communication. This creates a two-dimensional communication architecture: the front-channel for controller-to-master communication and the back-channel for master-to-slave communication. This dimensional addition allows efficient inter-memory sharing without compromising controller simplicity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Device complexity

If internal commands are transmitted through the command/address channel, then command transmission is simple, but channel bandwidth is consumed and controller intervention is required

Engineering Contradiction:
Improvecommand transmission simplicityVSAvoidchannel bandwidth utilization
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent extracts the internal command transmission function from the main command/address channel by creating a separate back-channel. This extraction allows internal master-to-slave commands to be transmitted independently without consuming front-channel bandwidth or requiring continuous controller intervention, thereby improving overall channel utilization efficiency.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10719467B2Semiconductor memory device for sharing inter-memory command and information, memory system including the same and method of operating the memory system
Publication Date: 2020.07.21 SAMSUNG ELECTRONICS CO LTD
  • US10719467B2 patent drawing
  • US10719467B2 patent drawing
  • US10719467B2 patent drawing

AI summary

A method of operating a memory controller, memory devices including a master memory device and slave memory devices, a back channel bus coupling the master memory device to the slave memory devices and a channel coupling the memory controller to the memory devices is provided as follows. A memory command is received by the memory devices from the memory controller. An internal command is generated and outputted by the master memory device. The internal command is received by the slave memory devices. The internal command is transmitted to the slave memory devices through the back channel bus.