Memory Background Refresh During Access Operations
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAM, experience downtime and increased power consumption due to the need for frequent refresh operations to maintain data integrity, which makes them unavailable for access operations.
Innovation Solution
Implementing background refresh operations that allow refreshes to occur concurrently with access operations, reducing the number of stand-alone refreshes by using refresh deficit counts to determine when and how to perform refreshes, and utilizing a controller to manage refresh commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional refresh operations are performed, then data integrity is maintained, but memory becomes unavailable for access operations and downtime increases
Solution Approach 1:
The patent merges refresh operations with access operations by allowing background refreshes to occur concurrently with ongoing access operations. The refresh control logic integrates refresh timing with access timing, enabling refresh operations to be performed during the row activation period without blocking access operations, thus eliminating downtime while maintaining data integrity.
Solution Approach 2:
The patent implements preliminary refresh actions by performing refresh operations before they would traditionally be needed. The refresh control logic monitors refresh counters and initiates background refreshes during row activation periods, proactively maintaining data integrity before potential data loss occurs, thereby eliminating the need for stand-alone refresh operations that would cause downtime.
2Reliability
If frequent refresh operations are performed, then data integrity is maintained, but power consumption increases
Solution Approach 1:
The patent combines refresh operations with access operations, allowing the memory device to perform refreshes during row activation periods without requiring separate stand-alone refresh cycles. This merging eliminates redundant refresh operations and reduces overall power consumption while maintaining data integrity through continuous background refreshes.
Solution Approach 2:
The patent ensures continuous useful action by maintaining background refresh operations that run concurrently with access operations. The refresh control logic continuously monitors and manages refresh timing to ensure data integrity is maintained without interrupting access operations, thereby eliminating wasted power from stand-alone refresh cycles while preserving reliability.
3Reliability
If stand-alone refresh operations are performed, then data integrity is maintained, but device complexity and operational overhead increase
Solution Approach 1:
The patent merges refresh control logic with access control logic, integrating both functions into a unified refresh control mechanism. This integration eliminates the need for separate stand-alone refresh operations and reduces operational overhead by handling both refresh and access timing through a single coordinated control approach managed by the refresh control logic.
Data Source
AI summary
A memory device receives a command, address, or combination thereof as part of an access operation which indicates an opportunity to perform a refresh background operation. The memory device may determine whether or not to perform the background refresh operation. If a background refresh operation is performed, the memory accesses a word line in a first section of a memory bank and refreshes a word line in a different section of the memory bank. In some embodiments, an opportunity background refresh operation may be signaled by an access command with an extended timing window.