Memory Background Refresh to Reduce Access Downtime
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices, particularly DRAM, face downtime and increased power consumption due to the need for frequent refresh operations, which make them unavailable for access operations.
Innovation Solution
Implementing background refresh operations that allow refreshes to occur on memory cells during access operations, reducing the number of stand-alone refreshes and minimizing downtime by using refresh deficit counts to determine when to perform refreshes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed to maintain data integrity in memory cells, then data reliability is improved, but device availability for access operations deteriorates
Solution Approach 1:
The system performs background refresh operations proactively before data decay becomes problematic. By continuously monitoring refresh deficit counts and initiating refresh operations in advance during access operations, the system prevents data integrity issues before they arise, eliminating the need for reactive stand-alone refresh operations that cause downtime.
Solution Approach 2:
The patent enables refresh operations to occur continuously during access operations through background refresh mechanism. Instead of stopping access operations for refresh, the system performs refresh operations in the background, maintaining continuous useful action (data access) while simultaneously maintaining data integrity through continuous refresh operations.
2Reliability
If frequent refresh operations are performed to prevent data decay, then data reliability is improved, but power consumption increases
Solution Approach 1:
The system implements feedback control by monitoring refresh deficit counts and only initiating background refresh operations when necessary. The refresh control logic uses feedback from access operation completion status and refresh deficit conditions to determine whether to perform refresh operations, avoiding unnecessary refresh operations that would consume power without improving data integrity.
Solution Approach 2:
The system performs partial refresh operations only when and where necessary, rather than performing full refresh operations continuously. By using refresh deficit counts to determine the exact scope and timing of refresh operations, the system applies partial action only to the extent needed to maintain data integrity, reducing overall power consumption.
3Reliability
If stand-alone refresh operations are performed to ensure data integrity, then data reliability is improved, but device productivity deteriorates
Solution Approach 1:
The patent merges refresh operations with access operations by performing background refresh operations during access operations. Instead of separating refresh operations as distinct stand-alone events that reduce productivity, the system combines refresh functionality into the access operation timeline, allowing both functions to execute simultaneously without sacrificing productivity.
Solution Approach 2:
The system introduces background refresh operations as an intermediary mechanism that bridges data integrity requirements with access operation continuity. The background refresh acts as an intermediary process that handles data integrity maintenance without blocking access operations, allowing both reliability and productivity goals to be achieved simultaneously.
Data Source
AI summary
A memory device receives a command, address, or combination thereof as part of an access operation which indicates an opportunity to perform a refresh background operation. The memory device may determine whether or not to perform the background refresh operation. If a background refresh operation is performed, the memory accesses a word line in a first section of a memory bank and refreshes a word line in a different section of the memory bank. In some embodiments, an opportunity background refresh operation may be signaled by an access command with an extended timing window.