Nonvolatile Memory Backing Wiring Kink Prevention
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Solution Overview
Problem
The existing manufacturing method for nonvolatile semiconductor memory with a twin MONOS structure faces issues with high resistance due to kink formation between the control gate electrode and the connection layer, which hinders the formation of a satisfactory backing wiring structure, leading to increased wiring resistance and potential breakage of connections.
Innovation Solution
A manufacturing method involving the formation of a thin first hard mask layer that covers the bottom and side surfaces of a concave portion between gate electrodes, preventing kink formation during etching and allowing for the formation of a satisfactory backing wiring structure by ensuring proper protection and exposure of the connection layer for silicide formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional manufacturing method is used without a hard mask layer, then the manufacturing process is simpler, but kink formation occurs between the control gate electrode and connection layer during etching, leading to high resistance and connection breakage
Solution Approach 1:
A hard mask layer is formed in advance on the connection layer before the etching process. This preliminary protective layer prevents direct etching damage to the connection layer, avoiding kink formation and ensuring reliable electrical connections between the control gate electrode and upper metal wiring.
Solution Approach 2:
The hard mask layer acts as an intermediary protective element between the etching process and the connection layer. It mediates the etching process by providing a sacrificial layer that protects the underlying connection layer from direct exposure to etchants, thereby preventing kink formation while allowing the etching to proceed for other structures.
2Manufacturing precision
If the connection layer is fully exposed for silicide formation, then silicide can be formed properly, but the connection layer becomes vulnerable to damage during subsequent processing steps
Solution Approach 1:
The hard mask layer is formed preliminarily on the connection layer before any etching or silicide formation processes. This ensures the connection layer is protected during processing, and selective removal of the hard mask layer later allows precise exposure of the connection layer surface for high-quality silicide formation without compromising the underlying connection layer.
Solution Approach 2:
The protective hard mask layer is segmented or selectively removed in specific regions where silicide formation is required. This segmentation allows the connection layer to be exposed precisely where needed for silicide formation while maintaining protection in other areas, achieving both high manufacturing precision and reliability.
Data Source
AI summary
A nonvolatile semiconductor memory comprises a first memory cell transistor, a second memory cell transistor, a connection layer, protrusion portions and a contact portion. The first memory cell transistor comprises a first gate electrode formed above a first channel region, and a second gate electrode formed on a side of the first gate electrode through an insulating film. The second memory cell transistor comprises a third gate electrode formed above a second channel region, and a fourth gate electrode formed on a side of the third gate electrode through an insulating film and facing the second gate electrode. The connection layer connects the second gate electrode and the fourth gate electrode. The protrusion portions are formed of a material different than that of the second and fourth gate electrodes, and are formed on both ends of the connection layer. The contact portion is formed on the connection layer.