Semiconductor Memory Backside Contact Layout for Low-Resistance Power Delivery
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration, reliability, and reduced complexity while maintaining low manufacturing costs and efficient power delivery networks.
Innovation Solution
The semiconductor memory device incorporates a substrate with a shared contact that electrically connects the source/drain and gate electrodes through a backside contact, eliminating the need for power and ground lines in the BEOL layer, and utilizes a power delivery network on the backside, reducing congestion and increasing contact sizes to lower resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power and ground lines are routed through the BEOL layer, then electrical connections are established, but contact congestion increases and manufacturing complexity increases
Solution Approach 1:
The patent moves the power and ground connections from the traditional planar BEOL layer routing to a vertical dimension by using backside contacts that penetrate through the substrate. This dimensional change eliminates the need for complex lateral routing in the BEOL layer, reducing congestion and manufacturing complexity while maintaining reliable electrical connections.
2Productivity
If contact size is reduced for high integration, then device density increases, but contact resistance increases
Solution Approach 1:
By transitioning from lateral contact expansion in the BEOL layer to vertical contact penetration through the substrate, the patent achieves low resistance connections without increasing the lateral contact footprint. The vertical path allows sufficient contact area for low resistance while maintaining small lateral dimensions for high integration density.
3Power
If more power delivery network lines are added, then power delivery capability improves, but manufacturing complexity and congestion increase
Solution Approach 1:
The patent simplifies power delivery network implementation by using vertical backside contacts that can be formed in a single etching and filling step, regardless of the number of power lines required. This eliminates the need for multiple lateral routing layers and reduces manufacturing complexity while maintaining the ability to provide sufficient power delivery capability.
Data Source
AI summary
A semiconductor memory device includes a substrate including first and second surfaces opposite to each other, a first active pattern on the first surface, a first channel pattern on the first active pattern and a first source/drain pattern connected to the first channel pattern, a gate electrode provided on the first channel pattern and extending in a first direction, the gate electrode adjacent to the first source/drain pattern in a second direction intersecting the first direction, a shared contact provided under the first source/drain pattern and the gate electrode and electrically connecting the first source/drain pattern and the gate electrode to each other, and a backside metal layer on the second surface.