Memory Cell Backside Power Routing for Lower RC Loading
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity and density of integrated circuits (ICs) lead to challenges in processing and manufacturing, particularly in managing power dissipation and improving circuit density and performance.
Innovation Solution
A metal line routing method is introduced, where a part of the metal layers is transferred to the wafer back-side, reducing routing loading and enhancing circuit density within the same chip area, thereby improving the RC performance of metal conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If metal layers are routed only on the front side of the wafer, then the routing process is simpler, but the routing loading is higher and circuit density is reduced
Solution Approach 1:
The patent applies dimensionality change by routing metal layers on both the front side and back side of the wafer, utilizing the third dimension (depth/thickness of the wafer) to distribute routing loads. This allows circuits to be divided into front-side circuits and back-side circuits, effectively increasing the available routing space and reducing congestion on any single layer.
2Productivity
If more metal layers are used on the front side to improve circuit density, then functional density increases, but metal line resistance and RC performance deteriorate
Solution Approach 1:
The patent segments the routing function by dividing metal layers into front-side metal layers and back-side metal layers. This segmentation distributes the routing load across multiple independent pathways, reducing the current density and resistance in individual metal lines while maintaining high overall functional density through parallel routing channels.
3Productivity
If functional density is increased by scaling down geometry size, then production efficiency improves, but power dissipation increases
Solution Approach 1:
The patent utilizes the back side of the wafer as an additional dimension for routing, which shortens the average current path length by allowing direct back-side connections. This reduces the resistive power loss (I²R) while maintaining the scaled-down geometry benefits for production efficiency.
Data Source
AI summary
A method for forming a memory device includes forming a first pull-up transistor, a first pull-down transistor, a first pass-gate transistor, a second pull-up transistor, a second pull-down transistor, a second pass-gate transistor over a substrate; forming a first bit line and a second bit line electrically connected to a source/drain epitaxy structure of the first pass-gate transistor and a source/drain epitaxy structure of the second pass-gate transistor; forming a word line electrically connected to gate structures of the first and second pass-gate transistors; removing the substrate to expose a source/drain epitaxy structure of the first pull-down transistor and a source/drain epitaxy structure of the second pull-down transistor; and forming a first power line electrically connected to the bottom surface of the source/drain epitaxy structure of the first pull-down transistor and electrically connected to the bottom surface of the source/drain epitaxy structure of the second pull-down transistor.