Memory Bad Block Control Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in inhibiting erasing and writing operations on bad blocks in NAND-type flash memory, which can lead to data corruption and hardware damage due to incorrect command issuance, especially when system software bugs occur.
Innovation Solution
A memory system with a control circuit that checks status data to determine if a memory block is defective, preventing operations on identified bad blocks by canceling inhibit commands and managing bad block information in dedicated areas, reducing the need for frequent data reading and improving system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the host apparatus frequently reads bad block information to prevent operations on bad blocks, then data corruption and hardware damage are prevented, but system performance deteriorates due to increased read operations
Solution Approach 1:
The patent applies preliminary action by pre-managing bad block information in dedicated memory areas during manufacturing or initial operation. The control circuit maintains status data indicating defective blocks in advance, so when write or erase commands are received, the system can immediately check the pre-stored status data without needing to frequently read bad block information during normal operations. This resolves the contradiction by preventing data corruption through advance preparation while maintaining system performance through reduced frequent reads.
2Productivity
If the system allows operations on potentially bad blocks to improve performance, then system performance improves, but the risk of data corruption and hardware damage increases
Solution Approach 1:
The patent introduces an intermediary mechanism - the control circuit with dedicated bad block management - that sits between the host apparatus and the memory blocks. The control circuit receives commands from the host, checks the status data of target blocks using pre-stored information, and decides whether to allow operations. This intermediary enables the system to maintain high performance by allowing operations on good blocks while preventing operations on bad blocks, thus resolving the contradiction between performance and reliability.
3Reliability
If the system implements comprehensive bad block management to prevent incorrect operations, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory system into distinct functional components: dedicated bad block management areas in the memory cell array, a control circuit with specific bad block detection functions, and a host apparatus interface. The status data for each block is stored in dedicated areas (first area for initial status, second area for updated status), separating bad block management from general memory operations. This segmentation achieves reliable bad block management while controlling complexity by organizing functions into modular, dedicated components.
Data Source
AI summary
A memory system includes a plurality of pins for connection to the outside of the memory system, one of the pins being configured to receive a command signal, a memory cell array including a plurality of first memory blocks and a second memory block in which status data indicating which of the first memory blocks is defective, is stored, and a control circuit configured to determine whether or not a first memory block targeted by the command signal is indicated as being defective in the status data. The control circuit allows an operation to be performed on the targeted first memory block in accordance with the command signal when the targeted first memory block is not indicated as being defective, and blocks the operation to be performed on the targeted first memory block when the targeted first memory block is indicated as being defective.