Semiconductor Memory Bad Block Marking via Internal Control Logic
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Solution Overview
Problem
Current semiconductor memory devices require extensive and costly testing processes to identify defective memory blocks, necessitating large-capacity test apparatuses and high-performance calculations to generate bad block information and repair mapping information, which increases test time and cost.
Innovation Solution
The semiconductor memory device incorporates a control logic that autonomously performs bad block marking, generates bad block information, and creates repair mapping information, storing these results in a Content Addressable Memory (CAM) area within the device, allowing for internal testing without external apparatuses, thereby reducing test time and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external test apparatuses are used to perform bad block marking and generate repair mapping information, then measurement precision and reliability are improved, but device complexity and test cost increase
Solution Approach 1:
The memory device performs bad block marking and repair mapping information generation autonomously using its own internal resources. The control logic executes test code within the device, stores bad block marking data in internal latches, and generates repair mapping information without requiring external test apparatuses, thereby reducing test cost and apparatus complexity while maintaining measurement precision
Solution Approach 2:
The testing function is extracted from external test apparatuses and integrated into the memory device itself. By incorporating the control logic, bad block latches, and test code execution capabilities directly into the device, the patent eliminates the need for large-capacity external test equipment while preserving the ability to accurately identify defects
2Measurement precision
If high-performance calculations are performed externally to generate bad block information and repair mapping information, then measurement precision is improved, but test time and loss of time increase
Solution Approach 1:
Test code is pre-stored in the memory device, and the control logic is pre-configured to execute the testing sequence. The bad block latches are pre-positioned to capture defect information as testing progresses. This preliminary preparation enables the device to perform calculations and generate repair mapping information internally without requiring time-consuming external processing
Solution Approach 2:
The device performs all calculation and information generation operations using its own internal control logic and resources. By self-generating bad block information and repair mapping information without external intervention, the device significantly reduces test time while maintaining the precision required for accurate defect identification
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a read/write circuit, and a control logic. The memory cell array includes a plurality of memory blocks. The read/write circuit performs a read/write operation on a selected page of the memory cell array. The address decoder stores bad block marking data on each of the plurality of memory blocks, and outputs the bad block marking data in response to an address signal. The control logic controls the read/write circuit to test whether a defect has occurred in the plurality of memory blocks, and controls the address decoder to store, as the bad block marking data, a test result representing whether the defect has occurred in the plurality of memory blocks.