Memory Device Bad Block Tagging and Isolation
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Solution Overview
Problem
Conventional memory devices cannot effectively disable memory blocks that become defective after deployment, leading to performance issues and interference with healthy blocks due to the lack of a mechanism to identify and isolate post-deployment bad blocks.
Innovation Solution
The implementation of a user-defined tagging mechanism that allows for the dynamic identification and disablement of bad memory blocks by disconnecting them from word lines and other circuits, using a separate deployment tag storage system to store addresses of bad blocks, and employing disable latches to prevent access and interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory blocks are accessed during normal operation, then productivity is improved, but defective blocks can cause harmful effects such as leakage currents and voltage collapses
Solution Approach 1:
The patent extracts and isolates defective memory blocks from the functional memory array by implementing a tagging mechanism that disconnects bad blocks from word lines. The tagging system separates defective blocks (identified by bad block tags in dedicated storage regions) from healthy blocks, allowing the former to be excluded from normal operations while preserving the productivity of functional blocks.
Solution Approach 2:
The patent introduces intermediary components including tag storage regions (separate from main memory), tag reading circuits, and control logic that mediate between the memory array and defective blocks. These intermediaries enable the system to identify, tag, and isolate bad blocks without disrupting normal memory operations, thereby eliminating harmful effects while maintaining productivity.
2Reliability
If a tagging mechanism is implemented to disable bad blocks, then reliability is improved, but device complexity increases due to additional storage and control circuits
Solution Approach 1:
The patent merges the tagging functionality with existing memory structures by implementing tag storage regions within the memory array framework and integrating tag reading/control functions into the existing memory control logic. This consolidation achieves reliable bad block isolation while minimizing additional complexity by reusing existing circuit resources rather than adding completely separate systems.
Solution Approach 2:
The tagging mechanism is designed with multi-functionality, where the same tag storage and control circuits serve multiple purposes: identifying bad blocks, disabling them from operations, and managing their isolation. This universal approach improves reliability through comprehensive block management while avoiding the complexity increase that would result from multiple dedicated systems.
Data Source
AI summary
A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.