Memory Bandwidth Estimation Circuitry for Controller Overload Prevention

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing computer architectures struggle to accurately throttle transaction sources based on transacted bandwidth, leading to potential memory controller overload and bus overutilization.

Innovation Solution

The implementation of bandwidth estimator circuitry to determine consumed bandwidth, which is used by rate limiter circuitry to throttle memory transactions, providing a more accurate representation of the memory controller's processing time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If transacted bandwidth is used to throttle transaction sources, then bandwidth control is implemented, but the accuracy of throttling is insufficient leading to memory controller overload

Engineering Contradiction:
Improvebandwidth measurement accuracyVSAvoidmemory controller overload prevention
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent replaces the conceptual 'transacted bandwidth' measurement with an actual 'consumed bandwidth' measurement system. The bandwidth estimator circuitry substitutes the theoretical bandwidth calculation with real measurement of bandwidth actually consumed by memory transactions, including overhead data. This substitution provides accurate measurement that enables reliable throttling control of transaction sources.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Ease of operation

If transacted bandwidth estimation is used, then throttling control is simplified, but actual processing time is not accurately represented

Engineering Contradiction:
Improvethrottling control simplicityVSAvoidmemory controller processing time accuracy
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent implements a feedback mechanism where the bandwidth estimator circuitry continuously measures the actual consumed bandwidth of memory transactions and feeds this information back to the rate limiter circuitry. The rate limiter uses this feedback to dynamically adjust throttling of transaction sources, ensuring that the throttling duration accurately reflects the actual processing time consumed by the memory controller, rather than relying on simplified estimates.

Inventive Principle:
Principle #23Feedback

3Productivity

If rate limiting is implemented without accurate consumed bandwidth measurement, then transaction flow is controlled, but memory controller overload occurs

Engineering Contradiction:
Improvetransaction throughput controlVSAvoidmemory controller overload prevention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements preliminary action by having the bandwidth estimator circuitry measure and determine the consumed bandwidth of each memory transaction before the rate limiter circuitry applies throttling. This preliminary measurement of actual consumed bandwidth (including overhead) allows the rate limiter to pre-calculate appropriate throttling durations, preventing memory controller overload before it occurs rather than reacting after overload has happened.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250181521A1Methods and apparatus to estimate consumed memory bandwidth
Publication Date: 2025.06.05 TEXAS INSTRUMENTS INC
  • US20250181521A1 patent drawing
  • US20250181521A1 patent drawing
  • US20250181521A1 patent drawing

AI summary

An example apparatus includes: bandwidth estimator circuitry configured to: obtain a first memory transaction; and determine a consumed bandwidth associated with the memory transaction; and gate circuitry configured to: permit transmission of the memory transaction to a memory controller circuitry; determine whether to gate a second memory transaction generated by a source of the first memory transaction based on the consumed bandwidth of the first memory transaction; and when it is determined to gate the second memory transaction, prevent transmission of the second memory transaction for an amount of time based on the consumed bandwidth.