Memory Controller Bandwidth Partitioning for Mixed-Criticality Timing
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Solution Overview
Problem
Modern multi-core chip platforms with shared memories suffer from memory interference, leading to timing unpredictability and hindering their use in applications requiring real-time responsiveness and determinism, such as automotive, avionics, and industrial automation, especially in mixed-criticality systems with different safety levels.
Innovation Solution
A memory controller that dynamically allocates and adjusts memory access bandwidth fractions to processing components based on timing information, distinguishing between critical and non-critical components to manage memory interference, using a Memory System Resource Partitioning and Monitoring subsystem.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processing units access shared memory simultaneously without control, then system productivity increases, but timing predictability deteriorates
Solution Approach 1:
The patent segments the shared memory bandwidth into separate dedicated bandwidths for different processing units (e.g., CPU bandwidth, GPU bandwidth, accelerator bandwidth). The memory controller independently manages each bandwidth, preventing interference between processing units while maintaining their individual access rights. This segmentation resolves the contradiction by allowing concurrent memory accesses without timing unpredictability.
Solution Approach 2:
The memory controller acts as an intermediary between processing units and shared memory. It receives memory access requests from multiple processing units, determines which unit has priority based on configured bandwidth allocations, and mediates the actual memory access by controlling the memory bus. This intermediary approach enables simultaneous productivity while guaranteeing timing predictability through controlled access arbitration.
2Reliability
If memory access is controlled to ensure timing predictability, then real-time responsiveness is improved, but device complexity increases
Solution Approach 1:
The memory controller dynamically adjusts bandwidth allocations based on real-time system conditions and priority levels. It can adaptively switch between different memory access control modes (e.g., round-robin, priority-based, bandwidth-limited) depending on the current workload and timing requirements. This dynamic control achieves real-time responsiveness without requiring overly complex static control mechanisms.
Solution Approach 2:
The system changes key parameters such as memory bandwidth allocation, access priority levels, and timing thresholds to achieve real-time responsiveness. The memory controller modifies these parameters based on system state, allowing flexible control without complex hardware architecture. By adjusting bandwidth fractions and timing parameters, the system achieves determinism while keeping the controller design manageable.
3Reliability
If dedicated bandwidth is allocated to each processing component, then timing predictability is improved, but memory access efficiency deteriorates
Solution Approach 1:
The memory controller implements periodic bandwidth reallocation cycles where it monitors memory access patterns and periodically adjusts bandwidth assignments. During normal operation, dedicated bandwidths maintain timing determinism. The controller periodically reviews system state and can reallocate bandwidth fractions to optimize efficiency based on current workload patterns, balancing determinism with performance.
Solution Approach 2:
The system performs preliminary bandwidth allocation at system initialization or when processing units are activated. The memory controller pre-configures dedicated bandwidth fractions for each processing unit based on their identified needs and priorities. This preliminary action ensures timing predictability is established before actual memory access begins, while the controller remains ready to optimize efficiency through subsequent adaptive adjustments.
Data Source
AI summary
A memory controller is provided and configured to control access to a memory with a memory access bandwidth by a plurality of processing components of a data processing system. The memory controller comprises a control unit configured to allocate a respective fraction of the memory access bandwidth to each of the plurality of processing components for accessing the memory by a plurality of memory access operations. Moreover, the memory controller comprises a monitoring unit configured to obtain timing information about a duration of a respective memory access operation by each of the plurality of processing components via a bus of the data processing system. The control unit is further configured to adjust, for one or more of the plurality of processing components, the respective fraction of the memory access bandwidth based on the timing information obtained by the monitoring unit.