Dynamic Memory Bandwidth Scaling via I/O Terminal Control
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Solution Overview
Problem
The limited bandwidth capacity of off-chip memory in computing apparatuses can lead to performance decline, especially when handling applications that require large data processing, and increasing bandwidth results in higher power consumption.
Innovation Solution
A method and apparatus that dynamically scale the bandwidth of external memory by activating or deactivating input and output terminals based on the dynamic context of a processor, such as cache miss rate or instructions per cycle, without altering voltage or frequency, using a bandwidth scaler that collects information and adjusts terminal usage accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bandwidth of external memory is increased to sustain high data transmission rates, then processor performance is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic bandwidth scaling by activating or deactivating I/O terminals based on real-time processor context (cache miss rate, instructions per cycle). The bandwidth is adjusted dynamically rather than being fixed, allowing the system to match bandwidth to actual workload demands. This resolves the contradiction by providing high bandwidth only when needed for performance-critical operations while reducing bandwidth and power consumption during low-demand periods
Solution Approach 2:
The patent changes the bandwidth parameter of the external memory interface based on processor performance metrics. By monitoring cache miss rates and instructions per cycle, the system adjusts the number of active I/O terminals, thereby changing the effective bandwidth parameter. This allows the system to optimize the trade-off between performance and power consumption by adapting the bandwidth parameter to current operational requirements
2Quantity of substance
If the bandwidth of external memory is increased to handle large data processing applications, then data transmission capacity is improved, but input and output memory power increases
Solution Approach 1:
The system dynamically adjusts the number of active I/O terminals based on actual data transmission requirements. When large data processing applications are detected (through cache miss rate and IPC metrics), more terminals are activated to increase data transmission capacity. When demand is lower, terminals are deactivated to reduce power consumption. This dynamic adaptation resolves the contradiction between transmission capacity and power consumption
3Productivity
If more input and output terminals are activated to expand bandwidth, then memory bandwidth capacity is improved, but power consumption by the computing apparatus increases
Solution Approach 1:
The patent applies partial action by activating only the necessary number of I/O terminals required to meet current bandwidth demands, rather than keeping all terminals active. The system determines the optimal number of terminals to activate based on processor context, using only the partial bandwidth needed for current workloads. This reduces power consumption while maintaining sufficient performance by avoiding excessive terminal activation
Data Source
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AI summary
A method for adjusting bandwidth, a bandwidth scaler and an apparatus are provided. The method for adjusting bandwidth involves determining a dynamic context of a processor, and based on the determined dynamic context, scaling bandwidth between the processor and a memory.