Memory Bank Access Circuit with Edge-Synchronized Address Comparison
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Solution Overview
Problem
Conventional memory devices face restrictions in bank accesses due to overlapping read and write operations at high clock speeds, requiring complex address comparisons and 'no operation' cycles to maintain proper operations, which limits access flexibility and efficiency.
Innovation Solution
The proposed memory device allows simultaneous access to multiple banks within a clock cycle without comparing addresses to previous cycles, enabling flexible operations by comparing bank addresses only on the falling edge of the clock cycle and allowing any bank access on the rising edge, thus eliminating the need for 'no operation' cycles and reducing restrictions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional address comparison methods are used to prevent overlapping read and write operations, then reliability is improved, but device complexity and access restrictions increase
Solution Approach 1:
The patent segments the address comparison function into two distinct parts: (1) comparison of read bank address with previous write bank addresses (performed on rising edge), and (2) comparison of write bank address with previous read bank addresses (performed on falling edge). This segmentation allows independent handling of read and write operations, reducing the complexity of simultaneous address comparisons while maintaining reliability by preventing overlapping operations on the same bank.
2Reliability
If conventional address comparison methods are used to prevent overlapping read and write operations, then reliability is improved, but access flexibility and productivity deteriorate
Solution Approach 1:
The patent performs address comparisons in advance at the appropriate clock edges: read bank address comparison is performed on the rising edge before the read operation, and write bank address comparison is performed on the falling edge before the write operation. This preliminary action ensures that address conflicts are detected and handled before the actual memory operations occur, maintaining reliability while enabling continuous operation without requiring 'no operation' cycles, thus improving productivity.
3Productivity
If clock speed is increased to improve productivity, then throughput is improved, but overlapping read and write operations cause reliability problems
Solution Approach 1:
The patent implements periodic address comparisons synchronized with the clock signal cycles. Address comparisons occur at specific periodic intervals: read bank address comparison on rising edges and write bank address comparison on falling edges. This periodic action ensures that at high clock speeds, address conflicts are systematically detected and prevented at each cycle boundary, maintaining reliability while allowing continuous high-speed operation without requiring insertion of NOP cycles.
4Reliability
If 'no operation' cycles are inserted to prevent overlapping operations, then reliability is improved, but access flexibility and productivity worsen
Solution Approach 1:
The patent performs address comparisons in advance at the appropriate clock edges (rising edge for read addresses, falling edge for write addresses) before the actual memory operations begin. This preliminary comparison allows the system to identify and prevent address conflicts before they occur, eliminating the need to insert 'no operation' cycles that would cause access latency. The preliminary action maintains reliability while preserving continuous operation and minimizing access time.
Data Source
AI summary
A method can include storing a plurality of addresses within one cycle of a timing clock, each address corresponding to a storage location of a memory device; and following the one cycle, accessing a plurality of banks of the memory device in response to the stored addresses corresponding to different banks and preventing access to any one of the plurality of banks by more than one address of the one cycle; wherein each bank includes memory cells arranged into rows and columns that comprise the storage locations.