Memory Bank Access Method Reducing Page Switch Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing DDR3 SDRAM technology experiences low access efficiency when switching between different pages within the same bank, resulting in significant latency and reduced performance.
Innovation Solution
The method involves dividing data blocks into subblocks and mapping them to different memory banks in ascending or descending order, optimizing the bank access sequence to maximize the time interval between accesses to the same bank, thereby reducing inter-page access operations and improving memory access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If contiguous memory access operations access different pages of a same Bank, then memory access operations can be performed, but a relatively long latency is needed between two read/write commands which severely reduces access efficiency
Solution Approach 1:
The patent segments a data block into multiple data subblocks and maps them to different memory banks. When switching between pages in the same bank is required, the system divides the access operations into smaller subblock units that can be distributed across multiple banks, thereby reducing the latency penalty associated with inter-page access in a single bank and improving overall memory access efficiency
Solution Approach 2:
The patent transitions from a single-dimension access pattern (one bank) to a multi-dimensional access pattern (multiple banks). By mapping data subblocks to different banks in ascending or descending order, the system exploits the additional bank dimension to avoid the latency bottleneck of same-bank page switching, thus improving access efficiency without sacrificing the ability to perform contiguous memory access operations
2Productivity
If data blocks are divided into subblocks and mapped to different banks, then memory access efficiency is improved, but the complexity of the memory access control increases
Solution Approach 1:
The patent performs preliminary actions by pre-dividing data blocks into data subblocks and establishing a mapping scheme to multiple banks before actual memory access operations. This preprocessing step, including determining the access sequence in advance (ascending or descending order by bank number), simplifies the control logic during execution by eliminating the need for complex real-time decisions, thus improving memory access efficiency while keeping the control complexity manageable
Solution Approach 2:
The patent introduces dynamic elements in the memory access control by allowing flexible selection of access sequences (ascending or descending order by bank number) and adapting the mapping strategy based on the number of available banks. This dynamic approach enables the system to optimize for different hardware configurations and access patterns without requiring a completely different control architecture, thereby improving efficiency while maintaining reasonable control complexity
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The present invention relates to a data processing method, apparatus, and system, so as to resolve a problem in the prior art that access efficiency is relatively low when two contiguous memory access operations access different pages of a same Bank. The data processing method includes: dividing a to-be-processed data block Block into multiple data subblocks, where a quantity of the multiple data subblocks is less than or equal to a quantity of banks Banks of a memory; and performing an access operation on a Bank corresponding to each data subblock of the to-be-processed Block, where different data subblocks of the Block are corresponding to different Banks of the memory. In an embodiment of the present invention, a processor maps different data subblocks of a to-be-processed Block to different Banks, so that a quantity of inter-page access operations on a same Block may be reduced, thereby improving memory access efficiency.