Multiprocessor Memory Bank Address Assignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multiprocessor systems face increased circuit complexity and lower operational speeds due to the use of lower-speed interfaces and single-port DRAMs, which hinder efficient data access and processing across multiple processors.
Innovation Solution
A method of assigning bank addresses in a semiconductor memory device with a memory cell array, where each processor has separate or shared access to memory banks through dual ports, allowing for optimized bank address allocation and improved data access efficiency across processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single-port DRAMs and lower-speed interfaces are used in multiprocessor systems, then device complexity is reduced, but operational speed and data access efficiency deteriorate
Solution Approach 1:
The memory system is segmented into multiple independent memory banks (Bank 0, Bank 1, Bank 2, Bank 3) that can be accessed simultaneously through different ports. This segmentation allows parallel data access operations, thereby increasing operational speed without proportionally increasing overall system complexity.
Solution Approach 2:
The patent introduces a new dimension of access by implementing dual ports (Port 0 and Port 1) on the same memory device, allowing simultaneous access from multiple processors. This dimensional addition enables parallel operations that significantly improve operational speed while maintaining reasonable device complexity.
2Device complexity
If single-port DRAMs are used, then device complexity is reduced, but data access efficiency across multiple processors deteriorates
Solution Approach 1:
The memory device is divided into multiple banks that can be independently accessed. When Port 0 accesses Bank 0 while Port 1 accesses Bank 1, both processors can simultaneously read or write data without interfering with each other, thereby dramatically improving data access efficiency while keeping the circuit design manageable through systematic segmentation.
Solution Approach 2:
The memory device is designed with universal dual-port functionality, where both Port 0 and Port 1 can access any of the memory banks. This multi-functionality allows flexible data access patterns and enables both processors to efficiently access required data simultaneously, enhancing overall productivity without requiring separate memory devices for each processor.
3Device complexity
If lower-speed interfaces are used internally, then device complexity is reduced, but operational speed deteriorates
Solution Approach 1:
By segmenting the memory into multiple banks accessible through dual ports, the system enables parallel data transmission operations. Multiple data words can be transmitted simultaneously through different ports and banks, thereby increasing overall data transmission speed while maintaining relatively simple interface circuits for each individual port.
Data Source
AI summary
A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.