Memory Bank Address Mapping for Read-Write Parallelism
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Solution Overview
Problem
Existing memory systems face inefficiencies in read and write operations due to high address decoding methods, which lead to blocking of requests and serial execution, reducing overall memory performance by preventing simultaneous read and write operations to the same physical memory bank.
Innovation Solution
Implementing a memory operation method that uses low address decoding to map consecutive logical addresses to different memory banks and an arbitration circuit to manage conflicts, allowing for parallel read and write operations by staggering requests and delaying write operations when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If high address decoding is used to map each physical memory bank to a large continuous logical address range, then the address mapping is simplified, but read and write requests with consecutive logical addresses are mapped to the same physical memory bank causing blocking and serial execution
Solution Approach 1:
The patent segments the address decoding process into high address bits for selecting memory banks and low address bits for selecting memory units within banks. This segmentation allows consecutive logical addresses to be distributed across different memory banks while maintaining simple address mapping within each bank.
Solution Approach 2:
The patent introduces a new dimension in address mapping by using low address bits (instead of only high address bits) to select memory banks. This dimensional change enables consecutive logical addresses to map to different physical banks, allowing parallel read and write operations without complicating the overall address mapping structure.
2Device complexity
If one physical memory bank has only one physical access interface, then the memory bank structure is simplified, but simultaneous read and write operations to the same memory bank become impossible requiring serial execution
Solution Approach 1:
The patent uses an arbitration circuit that performs preliminary arbitration on read and write requests before they reach the memory bank. This preliminary action determines priority and prevents conflicts before they occur, eliminating wait times while maintaining simple memory bank structure with single access interfaces.
3Reliability
If read and write requests are arbitrated when mapped to the same memory bank, then data access correctness is ensured, but the non-priority request must wait for the priority request to complete reducing parallelism
Solution Approach 1:
The patent introduces an arbitration circuit as an intermediary between the address decoders and memory banks. This mediator arbitrates conflicts based on request types and timing, ensuring data correctness while maximizing parallelism by allowing concurrent operations on different banks without unnecessary waiting.
Data Source
AI summary
Disclosed are a memory operating method, memory and electronic device. The memory complies with a read-write parallel protocol and includes a plurality of memory banks, and the method includes: sequentially mapping read and write transactions for consecutive logical addresses to different banks according to a predetermined transmission bit width by an address decoder, and arbitrating the read transaction and write transaction mapped to the same bank in a current clock cycle by an arbitration circuit, wherein in case that a specific low address bits of the logical address are the same, the read and/or the write transaction are mapped to the same bank. The disclosure avoids long-term occupation of a certain physical bank with specific low address decoding solution, thereby improving the execution efficiency of the read-write parallel protocol. Furthermore, an arbitration mechanism is introduced to arbitrate read and write conflicts for the same memory bank in each clock cycle.