Memory Bank Address Mapping for High Line-Rate Routers

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Solution Overview

Problem

Network routers face performance degradation and traffic handling issues due to increased line rates and traffic volume, as general-purpose processors struggle to scale with added functionalities, leading to potential failure in handling traffic at line rate.

Innovation Solution

A data processing device with a control block that performs logic operations on address bits to map requests across multiple memory banks, optimizing access patterns and spreading non-contiguous addresses across banks to maintain efficiency and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If general purpose processors are used in routers, then device complexity and ease of manufacture are improved, but processing speed and productivity deteriorate when handling increased line rates and network traffic volumes

Engineering Contradiction:

Improveease of manufactureVSAvoidprocessing speed

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The patent replaces the mechanical/software-based general purpose processor system with a hardware-based purpose-built router system. This substitution involves implementing dedicated hardware components including address mapping logic, memory banks, and control blocks that are specifically designed for routing operations, thereby achieving line rate processing performance while maintaining ease of manufacture through standardized hardware design approaches

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the operational parameters of the router by transitioning from software-execution modes to hardware-parallel processing modes. This includes changing the address access pattern from sequential to parallel through multiple memory banks, and changing the processing architecture from general-purpose sequential execution to purpose-built parallel hardware operations, thereby achieving both high productivity and ease of manufacture

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If new functionalities are added to software-based routers, then adaptability is improved, but processing speed and line rate performance deteriorate

Engineering Contradiction:

ImprovefunctionalityVSAvoidline rate performance

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent segments the router functionality into dedicated hardware modules including address mapping logic, multiple memory banks, and control blocks. Each segment is optimized for specific routing operations, allowing new functionalities to be added as separate hardware modules without impacting the performance of existing functions, thereby maintaining line rate performance while improving adaptability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent creates a universal hardware platform with purpose-built components that can handle multiple routing functionalities simultaneously. The address mapping logic and memory bank structure are designed to accommodate various routing protocols and functions (accounting, policing, forwarding) in parallel, enabling the system to maintain high speed performance while providing versatile adaptability

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Device complexity

If address bits are mapped directly to memory banks, then device complexity is reduced, but memory access efficiency deteriorates due to contention on the same banks

Engineering Contradiction:

Improveaddress mapping complexityVSAvoidmemory access time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent introduces an additional dimension to the address mapping by performing logic operations on multiple bits (high order bit and low order bit) to generate the memory bank address. This dimensional expansion transforms the simple direct mapping into a multi-dimensional mapping space, distributing accesses across more banks and reducing contention while maintaining manageable complexity through systematic logic operation rules

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20110254590A1Mapping address bits to improve spread of banks

Publication Date: 2011.10.20 HEWLETT PACKARD ENTERPRISE DEV LP

AI summary

A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors, where the request includes a first address. The control block may perform a logic operation on a high order bit and a low order bit of the first address to form a second address, identify one of the memory banks based on the second address, and send the request to the identified memory bank.