Memory Bank Allocation for Parallel Access and Fault Tolerance
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Solution Overview
Problem
Existing memory access methods for nonvolatile memories in microprocessors and microcontrollers face inefficiencies and dependencies, particularly in simultaneous and independent access by multiple units, which are critical for functional safety and security against external attacks.
Innovation Solution
A method and chip design that dynamically assign multiple memory controllers to memory banks, allowing independent and simultaneous access by enabling flexible and failure-tolerant allocation of memory banks to controllers during runtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory controllers are provided to enable simultaneous independent access to multiple memory banks, then productivity and functional safety are improved, but device complexity and space requirements increase
Solution Approach 1:
Each memory controller is designed to dynamically access any memory bank rather than being dedicated to a specific bank. The memory controller includes a bank selection unit that can selectively activate different memory banks based on current operational needs, allowing a single controller to serve multiple banks and enabling simultaneous independent access without requiring separate dedicated controllers for each bank.
2Productivity
If memory banks are subdivided into multiple independent banks for parallel access, then productivity and security are improved, but device complexity increases due to required controller architecture
Solution Approach 1:
The system implements dynamic bank selection where the memory controller can change which memory bank is active based on runtime conditions. The bank selection unit responds to selection signals that determine which memory bank should be accessed, allowing the system to dynamically reconfigure memory access patterns without hardware changes, thus enabling parallel operations with flexible control.
Solution Approach 2:
The memory system is divided into multiple independent memory banks, each capable of being independently activated and accessed. This segmentation allows parallel operations on different banks while the controller manages them through a unified interface, reducing the need for multiple complex controllers while maintaining independence of each bank.
3Reliability
If dedicated memory controllers are assigned to specific memory banks for independent access, then reliability and freedom from interference are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
A single memory controller is designed to universally access multiple memory banks through dynamic bank selection. The controller includes logic to selectively activate different banks based on selection signals, providing isolation and independence for each bank without requiring separate dedicated controllers, thus simplifying manufacturing while maintaining reliability.
Data Source
AI summary
A method for dynamically activating a plurality of memory banks by way of a plurality of memory controllers in a chip, each of the memory banks being able to be read and written to independently of the other memory banks and each of the memory banks being able to be activatable by multiple of the plurality of memory controllers in each case. The method includes receiving information about an operating state of the chip, dynamically producing assignments of memory controllers to the memory banks based on the operating state of the chip, and activating the memory banks by way of the memory controllers in accordance with the produced assignments.