In-Memory Arithmetic Units With Bank Allocation for Pipelined Processing
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Solution Overview
Problem
Current memory devices face challenges in efficiently performing arithmetic operations due to the need for separate processing hardware, which increases the burden on the computing system and requires methods to optimize arithmetic operation processing.
Innovation Solution
A memory device is designed with multiple in-memory arithmetic units that perform pipelined arithmetic operations, each allocated a set of memory banks, allowing them to operate at a frequency less than or equal to the product of the memory banks' frequency, with a clock divider, bank selector, and multiplexer to manage data access and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate processing hardware is added to a memory device for in-memory processing, then arithmetic operation capability is improved, but device complexity increases
Solution Approach 1:
The patent combines memory functions and arithmetic processing functions into a single memory device. Multiple memory banks are integrated with in-memory arithmetic units that can perform arithmetic operations directly on stored data, eliminating the need for separate processing hardware and reducing overall device complexity while maintaining arithmetic capability.
Solution Approach 2:
The memory device is designed with multi-functional in-memory arithmetic units that can perform various arithmetic operations (addition, multiplication, etc.) on data stored in memory banks. These units serve both as storage and processing elements, allowing the same hardware to fulfill multiple functions and reducing the need for dedicated separate processing components.
2Speed
If multiple memory banks are allocated to each in-memory arithmetic unit for simultaneous access, then processing speed is improved, but device complexity increases
Solution Approach 1:
The memory device is segmented into multiple independent memory banks, each capable of being accessed by in-memory arithmetic units. This segmentation allows parallel access to different data sets simultaneously, improving processing speed while maintaining manageable complexity through modular organization.
Solution Approach 2:
The patent introduces a new dimension of parallelism by allocating multiple memory banks to each in-memory arithmetic unit. This allows the system to access data from multiple memory banks simultaneously through different address lines and control signals, effectively increasing processing throughput without proportionally increasing arithmetic unit complexity.
Data Source
AI summary
A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.