Semiconductor Memory Bank Array Keep-Away Zone Timing Control
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Solution Overview
Problem
As semiconductor processes shrink, timing parameters in memory devices increase, leading to reduced semiconductor yield and efficiency in memory systems.
Innovation Solution
A semiconductor memory device with a control logic that dynamically sets a keep-away zone by deactivating memory cell rows based on a word-line, allowing for partial overlap of row cycles between sub-arrays, thereby compensating for increased timing parameters and enhancing parallelism efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor process is shrunk, then device size is reduced, but timing parameters increase leading to reduced yield
Solution Approach 1:
The memory device is divided into multiple bank arrays, each bank array into multiple sub-arrays, and each sub-array into multiple memory cell rows. This segmentation allows independent control of different regions, enabling selective activation and keep-away zone setting to optimize timing parameters for each segment while maintaining overall device functionality.
Solution Approach 2:
The control logic dynamically sets the keep-away zone based on the activated word-line position and address signals. The keep-away zone is not fixed but adapts to the current operation, allowing flexible adjustment of timing parameters to compensate for process shrink effects and maintain manufacturing precision.
2Manufacturing precision
If timing parameters are increased, then yield is reduced, but parallelism efficiency can be improved
Solution Approach 1:
While one sub-array is in the keep-away zone (deactivated), another sub-array can be activated and operated. This continuous operation across different sub-arrays maintains productivity by ensuring that memory operations never stop, even when some regions are restricted for timing optimization.
Solution Approach 2:
The control logic changes the operational parameters of different sub-arrays by dynamically setting the keep-away zone. This allows different timing parameters to be applied to different regions simultaneously, optimizing manufacturing precision for each region while maintaining overall system productivity through parallel operations.
3Manufacturing precision
If keep-away zone is set to compensate timing parameters, then timing control is improved, but device complexity increases
Solution Approach 1:
The control logic preliminarily determines the keep-away zone based on the address signal before actual memory operations begin. This preliminary setting of the keep-away zone allows timing parameters to be pre-optimized for the upcoming operation, simplifying the control during execution while maintaining manufacturing precision.
Data Source
AI summary
A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.