Memory Bank Transfer Bus for Parallel Low-Power Data Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face inefficiencies in data transfer between banks, requiring external buses and consuming significant power and time, especially in processing-in-memory (PIM) implementations where data operations span multiple banks.
Innovation Solution
The implementation of a bank-to-bank transfer (BBT) bus separate from the internal bus allows for parallel, optimized data transfer between memory banks, minimizing power consumption and transfer time by selecting the shortest path, thereby reducing reliance on external data buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data transfer between memory banks uses external buses, then data can be transferred between banks, but power consumption increases and transfer time increases
Solution Approach 1:
The patent divides the memory system into multiple banks (first bank, second bank, third bank, fourth bank) with dedicated transfer paths. Each bank can transfer data independently through the BBT bus to specific destination banks, enabling segmented parallel transfers that reduce overall power consumption and transfer time compared to sequential external bus transfers.
Solution Approach 2:
The patent introduces an intermediary BBT (bank-to-bank) bus that enables direct data transfer between memory banks without requiring external bus interfaces. This intermediary transfer mechanism reduces power consumption by eliminating external bus signaling and reduces transfer time by providing a dedicated internal pathway.
2Productivity
If data transfer between memory banks uses external buses, then data can be transferred between banks, but transfer time increases
Solution Approach 1:
The patent segments the data transfer operation into multiple parallel pathways through the BBT bus, allowing simultaneous transfers between different bank pairs (e.g., first bank to second bank, third bank to fourth bank). This segmentation enables pipelined operations that significantly increase data transfer throughput compared to sequential external bus transfers.
Solution Approach 2:
The patent adds a new dimension to data transfer by implementing a dedicated internal BBT bus architecture that operates independently from external bus interfaces. This dimensional addition creates a parallel transfer channel that increases data transfer speed without interfering with external memory operations.
3Productivity
If a separate bank-to-bank transfer bus is implemented, then parallel data transfer between banks is enabled, but device complexity increases
Solution Approach 1:
The BBT bus is designed as a universal transfer mechanism that can serve multiple functions: transferring data between any pair of banks, supporting both read and write operations, and enabling parallel transfers across multiple bank pairs simultaneously. This multi-functionality justifies the added complexity by providing a versatile platform that enhances productivity across various memory operations.
Solution Approach 2:
The patent implements dynamic control of the BBT bus through a controller that can selectively activate different transfer paths based on operational requirements. The bus architecture allows dynamic configuration of source and destination banks, enabling adaptive parallel processing that optimizes productivity for different workloads while managing complexity through intelligent control.
Data Source
AI summary
The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.