Bank-to-Bank Memory Bus for Low-Power Fast Data Transfer
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Solution Overview
Problem
Current memory systems face inefficiencies in data transfer between memory banks, requiring external buses and consuming significant power and time, especially when performing operations that span multiple banks.
Innovation Solution
Implementing a bank-to-bank transfer (BBT) bus separate from the internal bus, allowing for parallel and optimized data transfer between memory banks, minimizing power consumption and transfer time by selecting the shortest path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data is transferred between memory banks using external buses, then data transfer capability is provided, but power consumption increases and transfer time increases
Solution Approach 1:
The patent segments the data transfer function by creating a dedicated bank-to-bank transfer bus separate from the internal bus. This segmentation allows data to be transferred between memory banks through a specialized path that bypasses the external bus interface, thereby reducing power consumption while maintaining transfer capability.
Solution Approach 2:
The patent introduces an intermediary structure - the bank-to-bank transfer bus - that mediates data transfer between memory banks. This intermediary provides a direct connection between banks, eliminating the need to route data through external bus interfaces and reducing both power consumption and transfer time.
2Speed
If data is transferred between memory banks using external buses, then data transfer capability is provided, but transfer time increases
Solution Approach 1:
The patent segments the data transfer function by creating a dedicated bank-to-bank transfer bus separate from the internal bus. This segmentation allows data to be transferred between memory banks through a specialized path that bypasses the external bus interface, thereby reducing power consumption while maintaining transfer capability.
Solution Approach 2:
The patent introduces an intermediary structure - the bank-to-bank transfer bus - that mediates data transfer between memory banks. This intermediary provides a direct connection between banks, eliminating the need to route data through external bus interfaces and reducing both power consumption and transfer time.
3Productivity
If a separate bank-to-bank transfer bus is implemented, then power consumption is reduced and transfer time is reduced, but device complexity increases
Solution Approach 1:
The bank-to-bank transfer bus is designed with multi-functionality, serving both as a data transfer path and as a pathway for instruction retrieval. This universality justifies the added structural complexity by providing dual benefits: reduced power consumption and improved processing performance through faster data access.
Solution Approach 2:
The patent implements preliminary action by pre-establishing the bank-to-bank transfer bus structure before data transfer operations are needed. This advance preparation enables immediate high-speed data transfer between banks without requiring dynamic reconfiguration, thereby justifying the structural complexity through performance gains.
Data Source
AI summary
The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.