Memory Bank Buffer Circuit Wear Leveling Read Sequence
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Solution Overview
Problem
Existing memory devices face challenges in efficiently managing data during read sequences, particularly in maintaining data integrity and distributing write operations evenly to prevent wear leveling issues.
Innovation Solution
The memory device incorporates a buffer circuit to temporarily store data during read sequences, allowing for a self-reference read method that includes a reset operation to determine data stored in memory cells, and simultaneously performs wear leveling processing by writing data to a different bank, thereby integrating data write-back and wear leveling operations within the read sequence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is read from memory cells using traditional read methods, then read operations can be performed, but write operations must be performed separately to restore data and perform wear leveling, increasing total operation time
Solution Approach 1:
The patent combines the data restore operation and wear leveling write operation into a single integrated process. During the read sequence, after sensing the read data, the system automatically performs a write operation to restore the memory cell to a reference state and simultaneously writes the read data to a different bank for wear leveling purposes. This merging eliminates the need for separate restore and wear leveling operations, reducing total operation time while maintaining read performance.
2Reliability
If wear leveling processing is performed separately from read operations, then data can be distributed evenly across banks, but this increases power consumption due to additional write operations
Solution Approach 1:
The system performs wear leveling as a self-service operation during the read sequence. The read data that is sensed from the memory cell is automatically written to a different bank as part of the normal read restore process. This self-service approach ensures even data distribution across banks without requiring additional dedicated wear leveling operations, thereby reducing power consumption while maintaining data distribution evenness.
3Ease of operation
If traditional read methods are used without integrated write-back, then read operations are simpler, but data integrity may be compromised and requires separate restore operations
Solution Approach 1:
The system performs the write-back operation as a preliminary action immediately following the read operation within the same read sequence. After the read data is sensed and determined, the system automatically writes this data back to restore the memory cell to a known reference state before the next read operation. This preliminary restore action ensures data integrity is maintained without requiring complex external control or separate restore operations, keeping the system easy to operate while guaranteeing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data integrity by ensuring accurate read operations and extends the lifespan of memory cells by evenly distributing write operations, while also reducing the overall operation time and power consumption compared to traditional methods.
Implementation Method 1
A memory device is known in which a variable resistance element, such as a magnetoresistance effect element, is used as a memory element
Data Source
AI summary
According to one embodiment, a memory device includes: a first bank including a first memory cell; a second bank including a second memory cell; and a buffer circuit configured to temporarily stores data, wherein, during a read sequence for the first memory cell, the first bank is configured to: sense a first signal from the first memory cell, set the first memory cell to a reset state after the first signal is sensed, sense a second signal from the first memory cell in the reset state, determine first data stored in the first memory cell, based on the first signal and the second signal, and store the first data in the buffer circuit, and the second bank is configured to: write the first data in the buffer circuit to the second memory.