Bidirectional Memory Bank Buffers for Faster Segmented Signal Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory devices increase in capacity by adding more banks, the length of signal lines such as LDRW lines, digit lines, and word lines also increases, leading to higher capacitance and resistance, which slows down the operating speed of memory devices, creating a need for faster signal coupling methods without compromising capacity.
Innovation Solution
Implementing bidirectional buffers between segments of signal lines, such as LDRW lines, digit lines, and word lines, to facilitate faster data transfer without the need for decoding circuitry, thereby reducing circuitry requirements and enhancing signal coupling speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory banks is increased to enhance capacity, then the memory device capacity is improved, but the length of signal lines increases leading to higher capacitance and resistance which reduces operating speed
Solution Approach 1:
The patent divides each LDRW line into multiple segments with bidirectional buffers inserted between them. This segmentation breaks the long signal path into shorter segments, reducing the capacitance and resistance of each segment while maintaining the overall memory capacity through multiple banks.
Solution Approach 2:
Bidirectional buffers are introduced as intermediary components between segments of LDRW lines. These buffers act as mediators that can drive signals in both directions, reducing the burden on individual line segments and enabling faster signal coupling without compromising capacity.
2Quantity of substance
If the length of LDRW lines is increased to connect more banks, then the memory capacity is improved, but the capacitance and resistance of the lines increase which slows down data transfer
Solution Approach 1:
Long LDRW lines are divided into multiple shorter segments with bidirectional buffers inserted at intermediate points. This segmentation reduces the capacitance and resistance of each individual segment, thereby reducing the time required for data transfer while still connecting multiple memory banks to maintain capacity.
Solution Approach 2:
The bidirectional buffers enable dynamic signal routing in both directions along the LDRW line segments. This dynamic capability allows for more flexible and efficient data transfer, reducing the time penalty associated with longer line lengths needed for increased capacity.
3Device complexity
If conventional terminal data drivers are used to couple data through LDRW lines, then the circuit design is simple, but the increased line length requires more complex decoding circuitry and reduces operating speed
Solution Approach 1:
Bidirectional buffers are used to replace conventional unidirectional terminal data drivers and decoding circuitry. These buffers can operate in both directions (read and write), eliminating the need for separate decoding logic and reducing overall circuit complexity while improving operating speed through reduced signal line capacitance and resistance.
Solution Approach 2:
The patent extracts and eliminates the need for complex decoding circuitry by using bidirectional buffers that inherently handle both read and write operations. This removal of unnecessary decoding components simplifies the circuit design while simultaneously improving operating speed.
Data Source
AI summary
A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.