Semiconductor Memory Bank Activation Clock Delay
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Solution Overview
Problem
High-speed semiconductor memory devices require precise alignment of system and data clocks to ensure reliable operation, but variations in pressure, voltage, and temperature cause asynchronous delays, leading to potential misalignment and insufficient setup/hold times during initial training operations, especially when the number of activated banks changes.
Innovation Solution
A semiconductor memory device that adjusts the delay between the external data clock and internal data clocks based on the number of activated banks, using either a clock input unit to generate an internal data clock with varying delays or a clock phase mixing unit to phase-mix the external data clock, ensuring optimal data transmission timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the data clock frequency is doubled to input/output four data in one system clock cycle, then the data transmission speed is improved, but the phase alignment between system clock and data clock becomes difficult to maintain
Solution Approach 1:
The patent implements a dynamic phase adjustment mechanism where the phase of the data clock is continuously adjusted based on feedback from phase detection circuits. The system dynamically modifies the data clock phase to maintain proper alignment with the system clock, resolving the contradiction between high-speed operation and phase alignment reliability.
Solution Approach 2:
The patent employs feedback control through phase detection circuits that monitor the phase relationship between system clock and data clock. The detected phase information is fed back to adjust the data clock phase, ensuring reliable phase alignment is maintained even at doubled data clock frequency.
2Reliability
If interface training operation is performed to align clocks, then the phase alignment is improved, but the operation time before actual data transmission increases
Solution Approach 1:
The patent performs clock phase alignment through interface training operation before actual data transmission begins. By completing the necessary phase calibration in advance, the system ensures reliable clock synchronization is established prior to high-speed data operations, accepting the time trade-off for guaranteed alignment.
3Adaptability or versatility
If the number of activated banks changes, then the memory capacity utilization is improved, but the asynchronous delay varies causing timing issues
Solution Approach 1:
The patent implements dynamic delay adjustment in the data clock path based on the number of activated banks. When bank activation changes, the system dynamically modifies the data clock delay to compensate for varying asynchronous delays, maintaining precise timing alignment across different operational configurations.
Data Source
AI summary
A semiconductor memory device includes a plurality of banks, a clock input unit configured to receive an external data clock, an internal data clock generation unit configured to receive the external data clock from the clock input unit and generate an internal data clock by delaying the external data clock by a delay amount which changes in correspondence to the number of banks activated among the plurality of banks, and a data buffer unit configured to buffer a data signal in response to the internal data clock.