Memory Bank Processor Integration for Command Transfer Delays
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Solution Overview
Problem
In memory devices, controlling operations externally leads to inefficiencies due to transfer time bottlenecks, especially in IoT applications where multiple memory devices ingest data, resulting in reduced computing system performance.
Innovation Solution
Implementing a system processor resident on the memory device to perform local processing and control memory operations, reducing the need for external command transfers and enhancing processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory operations are controlled externally via bus transfers, then the memory device can be简单地 manufactured with basic memory cells, but command transfer time increases and processing performance decreases
Solution Approach 1:
The patent merges the processor and memory device into a single integrated unit, allowing the processor to be physically coupled to and directly control memory operations. This eliminates the need for external bus transfers for command execution, thereby reducing command transfer time while maintaining manufacturing feasibility through integrated circuit techniques.
Solution Approach 2:
The patent introduces a direct control path as an intermediary between the processor and memory device, bypassing the external bus system. This intermediary control mechanism enables rapid command transfer without requiring full bus protocol handshaking, thus reducing command transfer time while keeping the memory device structure relatively simple.
2Device complexity
If data is transferred externally for processing, then the memory device structure remains simple, but processing performance and computing efficiency are reduced
Solution Approach 1:
The patent combines the processor with the memory device to create an integrated processing-memory system. This merging allows data processing to occur directly within the memory device without external transfers, significantly improving processing performance while controlling overall system complexity through unified architecture design.
Solution Approach 2:
The patent shifts the processing dimension from external to internal by embedding the processor within the memory device structure. This dimensional change enables parallel processing operations to occur concurrently with memory operations, enhancing productivity without proportionally increasing device complexity.
3Ease of manufacture
If multiple memory devices ingest data externally, then each device can be manufactured independently, but system performance is reduced due to transfer bottlenecks
Solution Approach 1:
The patent merges processing capability with each memory device, enabling independent devices to perform local processing without external transfers. This maintains the advantage of independent manufacturing while eliminating transfer bottlenecks, as each device can autonomously process ingested data before system-wide aggregation.
Data Source
AI summary
An example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks.