Memory Bank Conflict Prevention via Variable Thread Latency
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Solution Overview
Problem
As the number of processor cores or function units increases, the likelihood of bank conflicts in memory systems also rises, leading to degraded processor performance due to frequent access disputes among memory banks.
Innovation Solution
A method and apparatus that determine the processing timing for each thread to access a memory bank, set variable latency for sequential access, and store threads in a data memory queue, allowing them to access the memory bank when their latency passes, thereby preventing bank conflicts by managing access priority and latency based on the number of stacks and fixed response time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processor cores or function units is increased, then the operation rate and processing performance are improved, but the probability of bank conflicts in memory increases
Solution Approach 1:
The patent applies dynamics by making the latency of thread accesses variable rather than fixed. The memory controller dynamically adjusts the latency of each thread based on the current state of the data memory queue and the response time of memory banks, allowing the system to adapt to varying access patterns and prevent bank conflicts while maintaining high processing performance
Solution Approach 2:
The patent changes the parameter of thread latency from a fixed value to a variable value that is adjusted based on system conditions. Specifically, the latency of each thread is modified according to the number of stacked threads in the data memory queue and the fixed response time of memory banks, thereby optimizing memory access timing to prevent conflicts
2Productivity
If multiple threads access the same memory bank simultaneously, then the operation throughput is improved, but bank conflicts occur causing processor stalling
Solution Approach 1:
The patent applies preliminary action by having the memory controller determine the processing timing and set the latency for each thread before the threads actually access the memory bank. Threads are scheduled in advance with appropriate latency values that prevent simultaneous access to the same memory bank, thereby preventing bank conflicts before they occur
Solution Approach 2:
The patent introduces a data memory queue as an intermediary between the function units and the memory banks. This queue buffers threads and allows the memory controller to manage their access timing, separating the high-throughput generation of memory requests from the constrained access to memory banks, thereby preventing conflicts while maintaining throughput
3Device complexity
If fixed latency is used for thread access, then the system complexity is reduced, but bank conflicts cannot be prevented effectively
Solution Approach 1:
The patent changes the latency parameter from fixed to variable, where each thread is assigned a specific latency value based on the current number of stacked threads in the data memory queue and the memory bank response time. This dynamic parameter adjustment enables effective bank conflict prevention without requiring complex arbitration logic
Data Source
AI summary
A method of preventing a bank conflict in a memory includes determining processing timing of each of threads of function units to access a first memory bank in which occurrence of a bank conflict is expected, setting a variable latency of each of the threads for sequential access of the threads according to the determined processing timing, sequentially storing the threads in a data memory queue according to the determined processing timing, and performing an operation by allowing the threads stored in the data memory queue to sequentially access the first memory bank whenever the variable latency of each of the threads passes.