Semiconductor Memory Bank Controller Timing Correction
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Solution Overview
Problem
Existing semiconductor memory apparatuses face challenges in ensuring timing margin accuracy, particularly at high frequencies, due to clock time variations, increased layout area, and unnecessary power consumption from column controllers.
Innovation Solution
The apparatus includes a bank controller that corrects the first address to match bank control timing, generating a second address for each bank, thereby eliminating the need for delay logic and reducing power consumption by latching the address until a new one is inputted.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If column controllers use delay logic to ensure timing margin according to clock timing, then timing margin is ensured, but layout area increases and manufacturing precision deteriorates at high frequencies
Solution Approach 1:
The patent replaces the mechanical clock-synchronized delay logic system with a timing correction system that operates independently of clock variations. The bank controller generates timing correction values based on actual timing requirements rather than relying on fixed delay logic synchronized to clock edges, thereby eliminating the trade-off between timing margin and address generation accuracy at high frequencies.
Solution Approach 2:
The patent dynamically adjusts timing parameters by generating correction values that compensate for timing variations. Instead of using fixed delay logic, the system changes timing parameters adaptively to ensure both timing margin and address generation accuracy, allowing the system to maintain precision across different operating frequencies.
2Reliability
If each column controller has delay logic for address generation, then timing control is achieved, but layout area increases
Solution Approach 1:
The patent merges the timing control function from individual column controllers into a centralized bank controller. Instead of each column controller having its own delay logic, the bank controller generates timing correction values for all banks, consolidating the timing control functionality and reducing the overall layout area while maintaining reliable bank control timing.
Solution Approach 2:
The bank controller serves multiple functions: it generates timing correction values, manages address generation, and controls multiple banks. This multi-functional approach replaces the specialized delay logic in each column controller, achieving timing control while reducing the total layout area through functional consolidation.
3Reliability
If column controllers operate continuously to control banks, then bank control is maintained, but power consumption increases
Solution Approach 1:
The patent implements periodic action by enabling column controllers only when bank selection occurs. The bank controller generates timing correction values and activates column controllers on-demand rather than maintaining continuous operation, thereby reducing power consumption while ensuring bank control continuity when needed.
Solution Approach 2:
The bank controller manages the operational state of column controllers, activating them only when required for bank selection operations. This self-service approach allows the system to maintain reliable bank control while minimizing power consumption by avoiding unnecessary continuous operation of column controllers.
Data Source
AI summary
An apparatus for controlling bank of a semiconductor memory includes a plurality of banks, a peripheral circuit unit that generates and outputs a bank selection signal and a first address, and a bank controller that generates a second address obtained by correcting the first address to match a bank control timing and outputs the generated second address to a bank corresponding to the bank selection signal among the plurality of banks. Since it is easy to ensure a timing margin, it is possible to completely prevent an address generation error, minimize a layout area, and reduce current consumption.