Memory Bank Group Data Bus Arbitration for Area Reduction
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Solution Overview
Problem
In high bandwidth memory systems, the large area required for multiple data buses poses a challenge in efficiently utilizing the data bus, leading to inefficiencies in data transfer operations.
Innovation Solution
The implementation of a memory system that alternates the use of two data buses (GIO_L and GIO_H) for read operations across different bank groups, with the bus control circuit managing the transfer signals to optimize data bus usage, allowing each bank group to use either the first or second data bus based on odd or even read commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple data buses are provided for each bank group, then data transfer capability is improved, but the area occupied by data buses increases
Solution Approach 1:
The patent merges the data bus resources by making bank groups share common data buses (GIO_L and GIO_H) instead of providing dedicated data buses for each bank group. This is achieved through a bus control circuit that manages arbitration and allocation of the shared data buses to different bank groups based on read commands, thereby reducing the total number of data buses required while maintaining data transfer capability.
Solution Approach 2:
The data buses GIO_L and GIO_H are designed to serve multiple bank groups universally. The same data buses are reused across different bank groups (e.g., bank groups A, B, C, D all share GIO_L and GIO_H), allowing these buses to perform multiple functions and serve multiple purposes, thus reducing the overall bus infrastructure area while preserving productivity.
2Area of stationary object
If the number of silicon through vias is reduced, then area is saved, but data bus efficiency may be compromised
Solution Approach 1:
The bus control circuit ensures continuous and efficient data transfer by implementing arbitration logic that continuously allocates the shared data buses to active bank groups. The circuit maintains uninterrupted data flow by switching between bank groups seamlessly, ensuring that the reduced number of data buses does not compromise overall data bus efficiency or productivity.
Data Source
AI summary
A memory includes: a first data bus; a second data bus; and a plurality of bank groups. The bank groups output read data by alternately using the first data bus and the second data bus during read operations of the bank groups. One of the plurality of bank groups transfer read data to the first data bus during a read operation based on an odd-numbered read command. Further, one of the plurality of bank groups transfer transfer one of the plurality of bank groups read data to the second data bus during a read operation based on an even-numbered read command.