Semiconductor Memory Bank Data Input Line Reduction
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Solution Overview
Problem
The increasing number of data input/output lines in semiconductor memory apparatuses due to higher operation speeds leads to increased chip area, which existing SerDes structures attempt to mitigate by pairing octet banks with data input/output lines, but this results in uneven data reception across banks, with some banks receiving data only every four clocks, causing inefficiencies.
Innovation Solution
A semiconductor memory apparatus with a control unit that generates control signals to synchronize command and address signals with a predetermined margin, allowing data to be efficiently inputted to paired octet banks through one data input/output line, ensuring balanced data reception across all banks by using a command address shifter, data enable signal generator, latch signal generators, and align signal generator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of operation speeds of semiconductor memory apparatuses is increased, then the number of data processed at a time increases, but the number of data input/output lines increases leading to increased chip area
Solution Approach 1:
The patent merges data transmission for multiple octet banks into a single data input/output line. Specifically, first and second octet banks share one data input/output line, allowing data to be transmitted alternately to both banks through the same physical line, thereby reducing the total number of data input/output lines required
Solution Approach 2:
The patent implements periodic data transmission to paired octet banks through a single data input/output line. Data is transmitted to the first octet bank during one clock cycle and to the second octet bank during the next clock cycle, creating a periodic pattern that allows efficient utilization of fewer data input/output lines
2Area of stationary object
If octet banks are paired to reduce data input/output lines, then the number of data input/output lines decreases, but data reception becomes uneven across banks with some banks receiving data only every four clocks
Solution Approach 1:
The patent introduces dynamic control through a control unit that generates different control signals for different octet banks based on their reception status. The control unit dynamically adjusts which octet bank receives data at each clock cycle, ensuring balanced data distribution across all banks despite using fewer data input/output lines
Solution Approach 2:
The patent implements a feedback mechanism where the control unit monitors data reception at each octet bank and adjusts control signals accordingly. When one octet bank has received sufficient data, the control unit directs subsequent data to the other octet bank in the pair, creating a feedback-driven load balancing system
Data Source
AI summary
A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin.