Memory Bank Compression and Merging for Efficient Data Output
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Solution Overview
Problem
Existing memory devices face challenges in efficiently handling increased data sizes due to the sharing of a fixed number of data lines among multiple memory areas, leading to increased circuit size and the need for new decoding methods when data is compressed, particularly in compression read operations.
Innovation Solution
The memory device is structured with multiple planes of memory banks, each grouped into bank groups, utilizing compressing circuits to compress data from multiple banks, merge circuits to combine compressed data, and an output buffer to transmit merged data to an external device, optimizing data handling during compression read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is compressed from multiple memory banks, then data transfer efficiency is improved, but circuit size increases
Solution Approach 1:
The patent merges compressed data from multiple memory banks into a single output data line. The merge circuit combines compressed data from first and second memory banks, allowing efficient utilization of the fixed number of data lines while maintaining compression benefits across multiple banks without requiring separate output lines for each bank.
Solution Approach 2:
The output buffer circuit serves multiple functions: it receives merged compressed data from the merge circuit, buffers the data, and outputs to external devices. This multi-functional design reduces the need for separate circuits for each function, thereby reducing overall circuit size while maintaining efficient data transfer.
2Device complexity
If multiple memory areas share a fixed number of data lines, then device size is reduced, but data transfer speed decreases
Solution Approach 1:
The patent implements time-division multiplexing where multiple memory bank groups share the data lines in predetermined time intervals. Each memory bank group is assigned specific time slots for data output, allowing efficient sharing of the fixed number of data lines while maintaining high transfer speeds through coordinated periodic access patterns.
Solution Approach 2:
The memory device is divided into multiple memory bank groups, with each group containing multiple memory banks. This segmentation allows parallel processing within groups while sharing data lines between groups through time division, effectively balancing device size constraints with data transfer speed requirements.
3Quantity of substance
If compressed data is output from multiple memory banks, then data compression ratio is improved, but decoding complexity increases
Solution Approach 1:
The merge circuit combines compressed data from multiple memory banks into a unified merged data stream before output. This merging process maintains the compression benefits while simplifying the decoding process at the external device, as the decoder receives a single consolidated data stream rather than multiple separate compressed streams requiring coordinated decoding.
Data Source
AI summary
A semiconductor device includes at least two planes including a plurality of memory bank groups, each of the plurality of memory bank groups including a plurality of memory banks, a plurality of compressing circuits, each coupled to at least two memory banks, the at least two memory banks being included in the same plane, each of the plurality of compressing circuits compressing a plurality of data read from the at least two memory banks to output compressed data, at least one merge circuit receiving a plurality of compressed data from at least two compressing circuits and merging the plurality of compressed data to output merged data, and an output buffer circuit receiving a plurality of merged data and outputting the plurality of merged data to an external device, wherein each memory bank, among the at least two memory banks, is included in different memory bank groups.